Introduction
As modern integrated circuit (IC) manufacturing scales into the sub-20nm regime, optical photolithography encounters fundamental physical limits governed by the Rayleigh diffraction barrier . The spatial resolution of a scanner is restricted by its wavelength and numerical aperture, preventing the direct printing of ultra-dense features required for modern logic and memory devices , . To extend the lifetime of existing lithography systems and sustain dimensional scaling, the semiconductor industry adopted multi-patterning techniques , . Among these, mandrel spacer patterning has emerged as a cornerstone technology for pitch division and feature density multiplication , .
The physical essence of mandrel spacer patterning lies in decoupling the critical dimension (CD) of final features from the lithographic limit of the exposure tool , . In this approach, a primary sacrificial template, known as a mandrel or mandrel core, is first defined using conventional lithography and etching , . Next, a highly conformal spacer material is deposited over the mandrel core , . An anisotropic etch-back process is subsequently performed to remove the spacer material from horizontal surfaces, leaving vertical sidewall spacers along the sides of the mandrel , . After the selective removal of the sacrificial mandrel core, the remaining self-aligned spacer loops serve as a high-resolution hard mask to pattern the underlying target layer, effectively doubling or quadrupling the spatial pattern density , .
This technology is commonly deployed as self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) , . Mandrel spacer patterning has transitioned from an experimental pitch-splitting technique to a mainstream manufacturing standard, enabling the fabrication of dense silicon fins and metallization lines in advanced technological platforms, such as the 14nm FinFET and 7nm FinFET nodes , .
Physics & Mechanism
The operational success of mandrel spacer patterning depends on three physical and chemical processes: isotropic conformal thin-film deposition, directional anisotropic plasma etching, and highly selective chemical removal of the mandrel core , , .
Conformal Spacer Deposition Physics
The physical thickness of the deposited spacer layer directly determines the CD of the final etched features . To minimize critical dimension uniformity (CDU) variation across a 300 mm wafer, the deposition process must achieve near-perfect conformality . Atomic layer deposition (ALD) is the primary technique used for spacer formation, relying on self-limiting, sequential gas-surface reactions .
Unlike transport-limited chemical vapor deposition (CVD) where deposition rates depend on precursor flux and diffusion gradients, thermal ALD operates in a surface-reaction-limited regime . In a typical ALD cycle, gaseous precursors are pulsed into the reaction chamber sequentially, separated by inert gas purges . The precursors chemisorb onto the active surface sites of the mandrel core until the surface is saturated . Because the reaction terminates once all surface sites are consumed, film growth is linear and extremely uniform over complex three-dimensional topologies , . Common spacer materials, such as silicon dioxide ($SiO_2$) or titanium dioxide ($TiO_2$), are deposited with atomic-scale control, translating directly into exceptionally low spatial CDU , .
Anisotropic Spacer Etch-Back Dynamics
Once the conformal spacer film is deposited, the horizontal layers must be selectively cleared while preserving the vertical sidewalls , . This is achieved using reactive ion etching (RIE) or inductively coupled plasma (ICP) RIE , . The physical mechanism of anisotropic etching is governed by the synergy of physical sputtering and chemical reactions under a directional electric sheath field .
Conformal Deposition Anisotropic Etch-Back Mandrel Pull (SADP)
[Spacer Film] [Ion Flux ||] [Spacer Mask]
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| || || | v v v v | | | |
| || || | =============> _ _ _ _ =============> | | | |
___| ||_|| |___ ___| | |___| | |___ ___| |___| |___
[Mandrel Core] [Mandrel Core] [Substrate]
In the plasma reactor, high-frequency electromagnetic fields generate a low-pressure discharge, producing reactive neutral radicals and positively charged ions . A negative bias voltage is applied to the electrostatic chuck, creating a plasma sheath field perpendicular to the wafer surface (Engineering Practice). Positive ions are accelerated across this sheath, bombarding horizontal surfaces at near-normal incidence . This physical bombardment transfers kinetic energy to the surface atoms, breaking chemical bonds and accelerating the reaction rate of chemical radicals with the spacer material to form volatile sub-products .
Conversely, the vertical sidewalls of the mandrel core experience negligible direct ion bombardment because the ion trajectories are parallel to the vertical surfaces , . Consequently, the etching of the vertical sidewalls is governed purely by spontaneous chemical etching, which proceeds at a significantly slower rate . This massive difference in vertical versus lateral etch rates allows the horizontal spacer film to be cleared, leaving behind isolated vertical spacer profiles on the sidewalls of the mandrel core , .
Selective Mandrel Core Removal
The final mechanical step of SADP is the removal of the sacrificial mandrel core without damaging the remaining spacers or the underlying hard mask template , . The core physical requirement for this step is high chemical etch selectivity . If the mandrel core is composed of an organic polymer, such as an amorphous carbon film or spin-on carbon, an oxygen-based ($O_2$) plasma ashing process is used , . The oxygen radicals react with the organic mandrel to form volatile carbon monoxide ($CO$) and carbon dioxide ($CO_2$) gases, which are swept out of the vacuum chamber, leaving the inorganic oxide or nitride spacers intact . If a silicon-based mandrel is used (such as amorphous silicon or polysilicon), halogen-based dry chemistries (utilizing chlorine or fluorine gas mixtures) are selected to achieve a rapid, highly selective chemical etch relative to the oxide spacer , .
Process Principles
Designing a robust mandrel spacer patterning scheme requires careful tuning of interdependent process parameters . The primary objective is to maximize the process window and minimize line edge roughness (LER), spacer pitch walking, and profile distortion , , .
Etch Bias and Mandrel Profile Control
The profile of the initial mandrel core dictates the structural integrity of the subsequent spacer , . The sidewall angle (SWA) of the mandrel core must be as close to vertical ($90^\circ$) as possible . If the mandrel SWA is tapered, the deposited spacer will inherit this slope (Engineering Practice). During the subsequent anisotropic etch-back, a tapered spacer profile undergoes rapid lateral erosion because the directional ions strike the sloped surface at an angle, leading to CD loss and profile asymmetry .
Furthermore, the initial width of the mandrel core must account for the etch bias of the mandrel patterning step . The physical size of the printed photoresist is typically larger than the target mandrel dimension . A controlled lateral trim etch is applied to reduce the mandrel width to the desired dimension before spacer deposition , . If the mandrel trim is insufficient, the final space between the two spacers will be too narrow, causing potential bridging or high aspect ratio profile distortion , .
Deposition Dynamics and Spacer Thickness Control
The thickness of the ALD spacer film is the primary control knob for the CD of the final trench or line , .
- Precursor Pulse and Purge Times: Insufficient purge times lead to gas-phase reactions between sequential precursors, causing parasitic CVD-like growth that degrades conformality and spatial thickness uniformity (Engineering Practice).
- Deposition Temperature: The temperature must be maintained within the ALD window of the precursor chemistry (Engineering Practice). Operating below this window can result in incomplete precursor decomposition and condensation, while operating above it leads to precursor desorption or thermal decomposition, both of which severely degrade film density and uniformity (Engineering Practice).
Spatial Critical Dimension Uniformity (CDU) and Pitch Walking
In SAQP, where two sequential cycles of mandrel-spacer-etch are executed, the final target patterns are formed by four distinct populations of spaces and lines , . Any systematic variation in the first or second spacer thickness leads to a failure mode known as pitch walking .
Normal Symmetric Pitch Pitch Walking (Asymmetrical Spacers)
| S1 | S2 | S1 | | S1' | S2' | S1' |
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The mathematical relationships governing the final spaces in a double-mandrel SAQP flow are highly sensitive to the deposition thickness of the first spacer ($d_1$), the second spacer ($d_2$), and the core mandrel width ($L_m$) :
- The space defined by the first spacer ($S_1$) is directly determined by the physical width of the first spacer loop .
- The space defined by the core mandrel ($S_2$) is a function of the mandrel core dimension after trimming .
- The gap space ($S_4$) is determined by the remaining distance between adjacent spacer loops .
To minimize the 3-sigma variation of these distinct space populations, the ALD process must maintain a thickness control capability of a fraction of a nanometer across the wafer . If the first spacer deposition is thicker than the nominal target, it systematically narrows the space defined by the second mandrel, creating alternating wide and narrow spaces across the layout .
Challenges & Failure Modes
Implementing mandrel spacer patterning at advanced technology nodes introduces complex physical, chemical, and mechanical failure modes , , .
Spacer Pitch Walking and Asymmetry
Pitch walking is the most prevalent systematic failure mode in multi-patterning . It is caused by any asymmetry in the spacer deposition or anisotropic etch-back steps , . If the spacer deposition has a directional bias, or if the RIE ions strike the wafer at a non-normal angle due to plasma sheath tilting or wafer edge effects, the spacer thickness on the left side of the mandrel will differ from that on the right . During pattern transfer, this asymmetry manifests as alternating line-space dimensions, degrading the electrical balance of transistors and interconnects .
Line Edge Roughness (LER) Transfer
Because the spacer is deposited conformally over the mandrel core, any high-frequency roughness or line edge perturbation on the mandrel is replicated on both the inner and outer boundaries of the spacer , . The LER and linewidth roughness (LWR) of the sacrificial mandrel core can be transferred directly into the final target features if not smoothed , . High LER increases local electric fields and scatter mechanisms in metal interconnects, accelerating electromigration failures and increasing line resistance , . Mitigation requires advanced post-lithography smoothing techniques, such as chemical trim reflow or optimized isotropic plasma etching .
Structural Pattern Collapse
As feature pitches shrink, the aspect ratio of the free-standing spacers increases dramatically . When the mandrel core is removed, the remaining spacers exist as tall, thin, isolated parallel lines , . During subsequent wet processing steps (such as cleaning with dilute hydrofluoric acid to remove native oxides), the capillary forces exerted by the drying liquid can pull adjacent spacers toward each other . If the mechanical strength of the spacer material is insufficient to withstand these surface tension forces, the spacers will bend, deflect, or collapse entirely, causing severe bridging defects and open-circuit failures , . This physical limitation imposes a strict constraint on the maximum permissible aspect ratio in any high aspect ratio process .
Normal Spacers Capillary-Induced Collapse
_ _ _ _
| | | | | | | <-- Spacers bend and touch
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Overlay-Induced CD Variation at Trim Cuts
To utilize SADP or SAQP in 2D random logic layouts, the continuous spacer loops must be cut at specific intervals to define distinct circuit nets . This is achieved using a secondary exposure known as a trim mask or cut mask . If there is an overlay error (misalignment) between the primary mandrel layer and the trim mask, the cut opening will be shifted . This displacement can cause partial cutting of adjacent active lines, leading to local line-width narrowing, increased resistance, or complete line-end shortening .
Technology Node Evolution
The implementation of mandrel spacer patterning has evolved dramatically as the semiconductor industry progressed through physical scaling milestones , , .
Node: 28nm 14nm/16nm 7nm and Beyond
Tech: Single Exposure (LELE / SADP) SADP (Fin/M1 Scaling) SAQP / EUV-SADP
Pitch: Larger Pitch (~80nm) Medium Pitch (~40-48nm) Ultra-dense Pitch (<30nm)
The 28nm Node: Introduction of Double Patterning
At the 28nm Planar Flow node, traditional single-exposure 193nm immersion lithography reached its limit for dense metal layers . While some manufacturers relied on litho-etch-litho-etch (LELE) schemes, SADP was introduced for critical 1D-like features . The primary advantage of SADP over LELE at 28nm was its self-aligned nature, which eliminated the overlay error accumulated between two independent lithography steps .
The 14nm/16nm Node: SADP as an Integration Standard
With the introduction of the FinFET architecture at the 14nm FinFET node, the spacing between silicon fins shrank beyond the single-exposure capability of immersion scanners . SADP became the industry-standard method to define the dense, parallel silicon fins . Additionally, the first metal interconnect layer (M1) adopted a "spacer-is-dielectric" (SID) SADP flow . In the SID approach, the spacer material acts as the inter-metal dielectric, allowing the formation of metal lines with highly uniform and customizable widths, while minimizing the risk of intra-layer short circuits .
The 7nm Node and Beyond: SAQP and the Transition to EUV
At the 7nm FinFET node, the target pitch for fins and critical metal layers shrank below 30nm . Because a single SADP cycle could not achieve this density from a 193nm immersion starting pitch, SAQP was adopted , . In SAQP, a first mandrel is patterned, spacers are formed, and the first mandrel is removed . The remaining spacers are then used as a second mandrel core to repeat the spacer deposition and etch-back cycle, resulting in a quadruple frequency multiplication of the initial lithographic pattern , .
When extreme ultraviolet (EUV) lithography was introduced to high-volume manufacturing, it initially simplified patterning by replacing multi-exposure immersion schemes with single EUV exposures (Engineering Practice). However, as scaling continued into the 3nm and 2nm nodes, the limits of single-exposure EUV resolution were also surpassed (Engineering Practice). Consequently, modern sub-3nm nodes combine EUV lithography with SADP or SAQP schemes (EUV-SADP/SAQP) to define the tightest pitches in the metal stack and active transistor channels, capitalizing on the superior CDU control offered by ALD spacer deposition .
Related Processes
Mandrel spacer patterning does not exist in isolation; it is highly integrated with several preceding and succeeding process steps in both front-end-of-line (FEOL) and back-end-of-line (BEOL) manufacturing .
Bottom Anti-Reflective Coating (BARC) and Hard Mask Stack
Before the mandrel core is lithographically defined, a complex material stack must be deposited on the wafer , . This typically includes a bottom anti-reflective coating layer beneath the photoresist to suppress light reflections and standing waves during immersion exposure, ensuring that the printed mandrel resist features have straight sidewalls and uniform dimensions . Additionally, a robust hard mask layer, such as spin-on carbon or amorphous silicon, is placed beneath the BARC to receive the trimmed photoresist pattern and act as the physical mandrel core during spacer deposition , .
Dummy Gate Integration and Transistor Formation
In FEOL processing, mandrel spacer patterning is used to define not only silicon fins but also the gate structures of advanced multi-gate transistors . During high-k metal gate integration, a sacrificial dummy gate (typically made of polysilicon) is defined using spacer lithography to ensure precise channel length control . The spacer on the sidewall of the dummy gate serves a dual purpose: it acts as a physical barrier to align the source/drain ion implantations and subsequently isolates the gate electrode from the adjacent source/drain contacts .
Gap Filling and Metallization
Once the spacer pattern is transferred into the target dielectric or silicon oxide layer, the resulting narrow, high-aspect-ratio trenches must be filled with conductive metal to form interconnects , . As the trench widths shrink below 15nm, standard copper physical vapor deposition (PVD) barrier/seed processes fail due to pinch-off and voiding . To achieve a void-free fill in these extreme structures, advanced metallization techniques, such as cyclic vapor-phase deposition of molybdenum or cobalt, or selective bottom-up direct metal growth, are employed to fill the spacer-defined gaps without creating reliability-limiting keyholes or voids , .
Future Outlook
As the semiconductor industry advances toward the sub-2nm node and transitions from FinFETs to nanosheet and forksheet architectures, mandrel spacer patterning continues to evolve to meet new physical challenges , .
Two-Color (Asymmetric) Spacers
Traditional SADP produces symmetric spacers of identical material on both sides of the mandrel core , . An emerging innovation is the "two-color" or asymmetric spacer design . By using oblique angle ion implantation, asymmetric deposition, or directional plasma etching, engineers can form a first spacer of one material (e .g., silicon oxide) on one sidewall of the mandrel and a second spacer of a different material (e .g., titanium oxide) on the opposite sidewall . Because these two materials possess completely different chemical etch selectivities, they can be addressed and removed independently during subsequent processing steps . This asymmetric capability dramatically reduces edge placement error (EPE) and provides layout designers with unprecedented flexibility when routing dense 2D logic libraries , .
Area-Selective Deposition (ASD)
To eliminate the complex and damage-prone spacer etch-back step, research is focusing heavily on area-selective deposition (ASD) . ASD utilizes chemical inhibitors or self-assembled monolayers to selectively prevent ALD growth on horizontal surfaces while allowing deposition on the vertical sidewalls of the mandrel core (Engineering Practice). This bottom-up approach could completely bypass the physical bombardment damage and profile rounding associated with RIE etch-back, delivering near-perfect rectangular spacer profiles with zero spacer-edge damage .
Direct Etch Metal Lines
To simplify the integration of BEOL metallization, patents have proposed utilizing vapor-phase metal deposition directly into the gaps defined by the spacers . In this scheme, metals like molybdenum or ruthenium are deposited into the high-aspect-ratio gaps, and the spacer material is subsequently stripped, leaving direct-etched, high-reliability metal lines without requiring traditional CMP-intensive damascene steps , . This shift from subtractive oxide patterning to direct metal patterning represents a significant paradigm shift in sub-2nm interconnect engineering , .