Technical Blog
Deep dive into the physics and integration logic of semiconductor manufacturing
Demystifying Poly Open Polish: Principles, Mechanisms, and Advanced Node Integration
In modern semiconductor manufacturing, the transition from conventional oxide-based gates to advanced transistor architectures has necessitated revolutionary changes in…
Pre-Litho Clean: Fundamental Principles, Chemical Mechanisms, and Node Evolution in Advanced Semiconductor Manufacturing
In the realm of ultra-large-scale integration (ULSI), surface cleaning is a continuous and critical necessity.
Fundamentals of Borophosphosilicate Glass (BPSG) in Semiconductor Manufacturing: Principles, Reflow, and Advanced Node Integration
In microelectronics fabrication, isolating active device regions while maintaining structural integrity over steep surface topography presents a fundamental challenge.
Deposition Rate: Meaning and Limits
Deposition rate measures film growth per unit time. Its trade-offs with coverage and film quality depend on method and geometry; the linked flow does not report rates.
Dielectric Anti-Reflective Coating (DARC): Principles, Optical Physics, and Advanced Integration
In modern semiconductor manufacturing, photolithography serves as the primary vehicle for pattern transfer, defining features that dictate device performance and density.
Diffusion Barrier: Copper Migration and Limits
A diffusion barrier limits copper migration from an interconnect into neighboring dielectric; protection, adhesion, and line resistance must be balanced.
Etch Back Principles, Integration Physics, and Technology Node Evolution
In the continuous scaling of integrated circuits, achieving planar, void-free, and highly reliable multi-layer structures is a primary objective of process integration.
Demystifying the Pre-Metal Dielectric: Physics, Process Integration, and Advanced Node Evolution
In the fabrication of modern integrated circuits, the boundary between active semiconductor devices and the complex network of metal interconnects represents a critical interface…
Self-Aligned Contacts: Selective Etching, Protective Boundaries and Integration
A self-aligned contact (SAC) uses retained dielectric protection and selective etching to open a source/drain connection while protecting the neighboring gate. Lithography still places the opening. Self-alignment provides tolerance to some pattern overlap; it does not eliminate overlay error or permit unlimited loss of the protective dielectric.
TEOS in Chipmaking: Oxide Precursor and Limits
TEOS is a liquid silicon precursor used in some oxide CVD routes. Film coverage and composition depend on oxidants, activation and geometry.
ArF Immersion Lithography: Physics, Process Principles, and Sub-10nm Scaling
For decades, the semiconductor industry has relentlessly pursued scaling to maintain the performance gains and cost reductions predicted by Moore’s Law.
Understanding CMP Slurry Abrasives: Physical Principles, Microscopic Mechanisms, and Advanced Node Integration
In modern semiconductor manufacturing, achieving global planarization across a wafer surface is a fundamental requirement for executing sub-resolution photolithography.