Pre-Litho Clean: Fundamental Principles, Chemical Mechanisms, and Node Evolution in Advanced Semiconductor Manufacturing

Introduction

In the realm of ultra-large-scale integration (ULSI), surface preparation is a continuous and critical necessity (Engineering Practice). Among these steps, pre-litho clean—the surface preparation process executed immediately prior to photoresist application and photolithographic exposure—serves as a primary gatekeeper for yield, defect control, and structural integrity [T1]. The primary goal of pre-litho clean is to systematically eliminate particles, organic films, and trace elemental contaminants from the wafer surface, creating an optimal surface state for chemical adhesion and subsequent patterning [T1].

As advanced semiconductor devices scale toward atomic dimensions, the tolerance for surface anomalies becomes virtually non-existent [T1]. Trace surface impurities, even at doses as low as $10^{9}$ atoms per square centimeter, can drastically modify interface physics, induce photoresist peeling, or block exposure light during advanced lithography sessions [T1], (Engineering Practice). To put this in perspective, a contamination density of this magnitude represents less than 0.0001% of an atomic monolayer [T1]. Consequently, wafer cleaning is the most frequently repeated sequence in modern integrated circuit manufacturing, interfacing with every major lithographic step [T1].

Historically, surface cleaning relied almost exclusively on liquid-phase wet chemistry, utilizing batch-immersion or single-wafer spray processors to dissolve and strip contaminants [T1]. However, the transition to complex three-dimensional architectures—such as the transition from planar transistors to the 14nm FinFET and 7nm FinFET nodes—has exposed the physical limitations of wet chemical transport in deep, high-aspect-ratio features [P2], (Engineering Practice). This has driven the industry to adopt a hybrid cleaning strategy that integrates advanced wet chemical recipes with dry chemical remote-plasma and sublimation techniques [P2], [A1]. Understanding the physical, chemical, and thermodynamic mechanisms of these cleaning methodologies is vital for process engineers optimizing yield across advanced technology nodes [P4].

Physics & Mechanism

To establish a highly clean, uniform surface, a pre-litho clean must address various contamination species using distinct physical and chemical mechanisms [T1]. Wafer contamination is broadly classified into three categories: organic films (such as photoresist residues), particulate contaminants, and trace metallic/oxide layers [T1].

Wet Chemical Oxidation and Solubilization

For organic contaminant stripping, wet cleaning processes leverage highly oxidative chemistries to chemically break down complex polymer chains into volatile gas species [T1]. The primary wet chemical blend utilized is the sulfuric acid-hydrogen peroxide mixture (SPM), which acts as a powerful oxidizer [T1]. SPM decomposes organic residues into carbon dioxide ($CO_2$) and water ($H_2O$) through aggressive oxidation pathways [T1].

Following organic stripping, the wafer is subjected to particle removal and inorganic cleaning, typically utilizing the standard clean 1 (SC1) and standard clean 2 (SC2) formulations originally developed by RCA [P4], [T1]. The SC1 chemistry, consisting of an ammonium hydroxide-hydrogen peroxide-water mixture ($NH_4OH/H_2O_2/H_2O$), operates via a dual-action mechanism [T1]:

1. Oxidation: Hydrogen peroxide ($H_2O_2$) continuously oxidizes the exposed silicon substrate, forming a thin, controlled native silicon dioxide ($SiO_2$) layer [A3].
2. Etching: Ammonium hydroxide ($NH_4OH$) slowly etches this regenerated $SiO_2$ oxide film (Engineering Practice).

This simultaneous oxidation-and-etching cycle generates a 'self-cleaning' effect that lifts off particles trapped on or within the surface oxide layer [P1], [T1]. Furthermore, SC1 raises the pH of the cleaning bath, which alters the Zeta potential of both the silicon surface and the suspended particles, inducing a mutually repulsive electrostatic force that prevents particle re-deposition [T1].

Conversely, the SC2 chemistry—a hydrochloric acid-hydrogen peroxide-water mixture ($HCl/H_2O_2/H_2O$)—is designed to target trace metallic impurities [T1]. Hydrochloric acid ($HCl$) acts as a strong complexing agent, reacting with alkali and transition metal ions to form highly soluble, stable metal-chloride complexes that are easily rinsed away, preventing metal-induced defect states in the active area [T1].

Wet Native Oxide Stripping

To achieve an atomically clean, native oxide-free surface, dilute hydrofluoric acid (DHF) is utilized [P1]. The selective dissolution of $SiO_2$ in DHF is driven by the high affinity of fluorine for silicon [P1]. The chemical reaction proceeds as follows:

$$SiO_2 + 6HF \rightarrow H_2SiF_6 + 2H_2O$$

Here, fluoride ions ($F^-$) break the polar $Si-O$ bonds, converting the oxide into soluble hexafluorosilicic acid ($H_2SiF_6$) (Engineering Practice). Following the DHF step, the silicon surface is left hydrogen-terminated ($Si-H$), rendering it highly hydrophobic and temporarily passivated against immediate re-oxidation in air [P1].

Dry Chemical Oxide Removal and Sublimation

In deep, high-aspect-ratio contact structures, wet cleans face severe surface tension limitations, preventing effective chemical delivery and causing structural collapse [P4]. Dry chemical cleaning processes, such as Siconi™ technology, bypass these limitations using gas-phase remote-plasma chemistry [P2], [A1].

In a typical Siconi™ pre-clean, a remote plasma of nitrogen trifluoride ($NF_3$) and ammonia ($NH_3$) generates active ammonium fluoride ($NH_4F$) and ammonium bifluoride ($NH_4HF_2$) species [P2], [A1]. These gaseous reactants selectively adsorb onto the native oxide surface at low temperatures, reacting with the $SiO_2$ layer to synthesize solid ammonium hexafluorosilicate ($(NH_4)_2SiF_6$) salt [P2]:

$$SiO_2 + 4NH_4F + 2HF \rightarrow (NH_4)_2SiF_6 + 2NH_3 + 2H_2O$$

Because this chemical reaction is highly selective to $SiO_2$, the underlying silicon substrate remains untouched, preventing lattice damage [P2]. Following salt formation, the wafer is transferred to an integrated annealing chamber where the temperature is ramped up to induce thermal sublimation [P2]. This thermally driven process decomposes the solid salt byproduct into volatile gases that are continuously evacuated by the vacuum system [P2]:

$$(NH_4)_2SiF_6(s) \rightarrow SiF_4(g) + 2NH_3(g) + 2HF(g)$$

Advanced Sublimation and Halogen Passivation for Si/Ge Surfaces

For advanced channels utilizing germanium (Ge) or silicon-germanium (SiGe) alloys, oxide removal is exceptionally complex due to the unstable nature of germanium oxide ($GeO_2$) [A2], [A3]. Modern pre-cleans utilize halogenation-based dry cleaning processes where halogens react with mixed oxides to form volatile halides with distinct sublimation temperatures [A2], [A3]. The sublimation behavior of these pre-clean materials follows the Arrhenius sublimation rate equation:

$$R = R_0 e^{-E_a/kT}$$

where $R$ is the sublimation rate, $R_0$ is the pre-exponential factor, $E_a$ is the activation energy of sublimation, $k$ is the Boltzmann constant, and $T$ is the absolute substrate temperature [A2].

To clean Si/Ge interfaces without damaging the substrate, a multi-step thermal process is employed [A2], [A3]. First, a halogen-containing pre-clean material is deposited at a low temperature to react with the oxide [A3]. Next, the temperature is ramped to preferentially sublime the silicon-containing halide species, exposing the silicon surface while the germanium-containing halide remains stable [A2], [A3]. Immediately following this exposure, a chlorine-containing gas is introduced to form a stable, low-temperature chlorine (Cl) passivation layer [A2], [A3]. This passivation layer lowers the surface free energy and blocks surface re-oxidation and contamination during subsequent thermal transitions [A2], [A3]. Finally, the wafer temperature is ramped higher to sublime both the chlorine passivation layer and the remaining germanium-containing halides, yielding a pristine, defect-free Si/Ge interface ready for subsequent processing [A2], [A3].

Process Principles

Optimizing a pre-litho clean requires a precise understanding of how process parameters directionally influence chemical kinetics, etch selectivity, surface roughness, and defect density [P2].

Process Parameter	Direction of Change	Resulting Impact on Film & Substrate	Performance Implications	References
Etching/Sublimation Temperature	Increase	Accelerates chemical kinetics; increases oxide sublimation rate	Reduces thermal budget requirements; risk of increased surface roughness and non-uniform etching	[P2], [P4], [A2]
HF/Fluoride Concentration	Increase	Increases native oxide etch rate	Improves throughput; risk of isotropic over-etching of field oxides and critical dimension (CD) swelling	[P1], [P2], [A1]
Oxidant Ratio ($H_2O_2$ in SC1/SC2)	Increase	Accelerates native oxide regeneration; enhances metal complexation	Improves surface passivation and metal particle removal; risk of excessive chemical oxide regrowth	[P1], [P4], [T1]
Process Exposure Duration (DHF/SC2)	Increase	Promotes complete removal of complex oxide residues and metal ions	Minimizes metallic and organic defect density; risk of extensive field oxide recess and dopant precipitation	[P1], [P4]
Remote Plasma Power / Radical Flow	Increase	Raises active radical ($NH_4F$) density on the substrate	Enhances dry oxide etch rate; potential for physical sputtering damage if ion shielding is compromised	[P2], [A1]

Thermal Effects and Reaction Kinetics

In dry cleaning processes, such as Siconi™, temperature control is exceptionally critical [P2]. The initial remote plasma reaction step must be conducted at low temperatures to promote the adsorption and condensation of reactive species onto the native oxide [P2]. If the wafer pedestal temperature rises even slightly above the set point, the condensation kinetics are disrupted, causing a significant reduction in the oxide etch rate [P2]. Conversely, the sublimation step requires high thermal uniformity across the wafer; temperature non-uniformity during annealing translates directly into incomplete byproduct removal and localized surface defects [P2], [A2].

In wet cleaning systems, temperature directly scales the reaction rate of chemical oxidation and etching [T1]. Higher temperatures in SC1 and SC2 baths accelerate organic decomposition and metal complexation, but this must be balanced against chemical decay (e [P4].g., thermal decomposition of $H_2O_2$ into $H_2O$ and $O_2$) and the risk of localized substrate pitting [A3].

Chemical Concentration and Mass Transport

For wet cleaning, the concentration ratio of the chemical bath dictates the etching and oxidation rates [T1]. In DHF steps, increasing the HF concentration accelerates native oxide removal but also increases the isotropic etch rate of surrounding dielectric structures, such as shallow trench isolation (STI) oxides [P1]. In dry remote plasma cleaning, the gas flow ratio of $NH_3$ to $NF_3$ determines the stoichiometry of the generated active species [P2], [A1]. A higher flow of $NF_3$ increases the fluorine radical density, which must be carefully modulated to avoid non-selective etching of adjacent silicon nitride spacers [T1].

Process Duration and Surface Energy Modification

The duration of the cleaning step is a primary driver of surface morphology [P4]. Extending the soak time of the final cleaning step (e (Engineering Practice).g., in a modified SC2 process) allows complete dissolution of metal ions and systematically minimizes micro-roughness [P4]. This reduction in surface roughness is crucial for epitaxial or molecular beam processes, as it significantly lowers the subsequent thermal cleaning temperature required to achieve an atomically flat surface [P4].

Furthermore, the cleaning duration directly determines the chemical termination of the surface (Engineering Practice). A long DHF-last clean ensures a fully hydrogen-terminated, hydrophobic surface (Engineering Practice). While this protects the silicon from oxidation, a highly hydrophobic surface can lead to poor wetting of polar photoresists, necessitating the downstream use of adhesion promoters such as hexamethyldisilazane (HMDS) to modify the surface free energy prior to spin-coating [P2].

Challenges & Failure Modes

Implementing a robust pre-litho clean process is associated with several severe physical and chemical failure modes that can directly impact device yield and electrical reliability [P2].

Dopant Out-Diffusion and Defect Precipitation

A critical failure mode occurs when DHF is used as a final cleaning step on heavily doped substrates, such as arsenic-implanted regions [P1]. During the ion implantation process, dopants are introduced into the silicon lattice and the adjacent field oxides (such as STI) [P1]. When the wafer is exposed to a DHF pre-clean, the HF chemically etches the arsenic-implanted field oxide [P1]. This chemical dissolution releases the underlying arsenic dopants from the oxide matrix, causing them to diffuse out and precipitate onto the silicon or oxide surface as insoluble arsenic oxide residues [P1].

$$\text{Arsenic-doped } SiO_2 \xrightarrow{DHF} H_2SiF_6 + \text{Precipitated Arsenic Oxides } (As_2O_3, As_2O_5)$$

If these arsenic residues are not removed, they act as physical barrier layers during subsequent metallization or silicidation, preventing direct contact between sputtered metals (e [P1].g., cobalt or titanium) and the silicon substrate [P1]. This leads to localized silicidation failures, resulting in open contact chains and high contact resistance [P1]. To mitigate this, process engineers utilize peroxide-containing cleans (such as SPM or SC2) after the DHF step [P1]. The strongly oxidizing peroxide environment regenerates a thin chemical oxide, lifting the arsenic precipitates off the surface via a self-cleaning mechanism and leaving a clean, residue-free interface [P1].

Isotropic Etching and Critical Dimension Swelling

In advanced nodes, contact holes and trench structures have extremely tight critical dimensions [P2]. Because chemical cleans—both wet DHF and dry Siconi™—are inherently isotropic, they etch oxides in all directions with equal velocity [P2], (Engineering Practice). When multiple Siconi™ cycles or extended wet cleans are applied to ensure complete oxide removal at the bottom of a contact hole, the chemistry simultaneously etches the vertical oxide sidewalls [P2]. This leads to CD swelling, where the lateral dimensions of the contact hole expand beyond design specifications, risking electrical shorting between adjacent features [P2].

Substrate Over-Etching and Surface Roughening

In dry halogen-sublimation processes used for mixed Si/Ge substrates, precise control of the temperature and gas dosing is mandatory [A3]. If the sublimation temperature is set too high, or if the halogen exposure time is excessively long, the cleaning chemistry can transition into an active substrate etchant [A2], [A3]. This results in substrate over-etching and non-uniform surface reactions, which dramatically increase surface roughness [A3]. High surface roughness degrades carrier mobility in the channel due to surface roughness scattering and leads to non-uniform electric field distribution in the gate dielectric [P4].

Queue-Time Re-Oxidation and AMC Adsorption

Following a pre-litho clean, the wafer surface is highly reactive [P1]. The queue-time (Q-time)—the duration the wafer spends in the cleanroom environment before entering the lithography track or deposition chamber—is a critical process window [A3], (Engineering Practice). During this window, oxygen and moisture in the ambient air can cause rapid native oxide regrowth, while volatile organic compounds in the cleanroom environment deposit onto the wafer as airborne molecular contaminants (AMCs) [P4]. AMCs degrade photoresist adhesion, leading to resist peeling or pattern collapse during exposure and wet development (Engineering Practice). If the wafer is transitioning to a deposition tool, this uncontrolled re-oxidation increases interface states and contact resistance, requiring strict Q-time controls or the integration of nitrogen-purged wafer transfer pods [A3], (Engineering Practice).

Technology Node Evolution

The evolution of cleaning technology across major technology nodes reflects the increasing complexity of semiconductor architectures and materials [P4].

28nm Planar Node

At the 28nm Planar Flow node, the device architecture was entirely two-dimensional [P4]. Cleaning strategies relied primarily on standard RCA wet chemistry (SC1 and SC2) coupled with automated wet benches [P4], [T1]. The aspect ratios of features were relatively low, allowing liquid chemicals to easily wet the surfaces, remove contaminants, and be completely cleared during the deionized water rinsing and isopropyl alcohol drying steps [T1], (Engineering Practice). Particle removal was assisted by mega-sonic agitation in wet baths, which provided sufficient physical force to overcome particle adhesion without damaging the planar structures (Engineering Practice).

14nm FinFET Node

The transition to the 14nm FinFET node introduced three-dimensional vertical fin structures with high aspect ratios [P2]. This transition exposed two major limitations of wet cleaning (Engineering Practice):

1. Capillary Force-Induced Damage: Megasonic physical agitation and wet drying techniques generated capillary forces that caused physical bending and collapse of the fragile vertical silicon fins (Engineering Practice).
2. Mass Transport Limitations: Surface tension prevented wet chemicals from fully penetrating and wetting the deep, narrow trenches between fins, leaving native oxides and contaminants intact at the bottom of the structures (Engineering Practice).

To overcome these issues, the industry transitioned to dry chemical cleans, such as Siconi™, for critical pre-contact and pre-silicidation steps [P2]. These dry, gas-phase chemical reactions eliminated capillary forces entirely, allowing damage-free, highly isotropic native oxide removal in deep 3D features [P2].

7nm FinFET Node and Beyond

At the 7nm FinFET node and beyond, the introduction of extreme ultraviolet (EUV) lithography and alternative high-mobility channel materials (such as SiGe and pure Ge) completely redefined pre-clean requirements [A2], [A3], (Engineering Practice). EUV lithography utilizes extremely thin photoresist layers because EUV photons have high absorption in organic materials (Engineering Practice). These ultra-thin resists are highly sensitive to surface energy variations and trace contaminants, requiring absolute uniformity in the pre-litho clean to prevent nanoscale defect projection and line-edge roughness [P2].

Furthermore, the chemical instability of SiGe and Ge channel materials prevented the use of aggressive wet chemistries, which would non-selectively etch and roughen the channel [A1], [A2]. This catalyzed the development of advanced dry pre-cleans featuring cyclic halogenation, selective sublimation, and in-situ chlorine passivation to clean the complex Si/Ge oxides at an atomic-scale without degrading the underlying channel architecture [A2], [A3].

Related Processes

Pre-litho clean does not operate in isolation; it is a highly integrated process step that directly impacts and is impacted by adjacent manufacturing processes [P1].

[Dry Etching / Ion Implantation] 
               │ (Generates polymers, residues, and dopant damages)
               ▼
       [Pre-Litho Clean] 
               │ (Removes residues, passivates surface, tunes surface energy)
               ▼
 [Epitaxy / Thin Film Deposition (ALD/CVD)] 
               │ (Requires pristine, defect-free, unoxidized interface)
               ▼
   [Rapid Thermal Annealing (RTA)] 

Ion Implantation

Ion implantation introduces dopants directly into the silicon lattice, which dramatically alters the chemical etch rates and reactivity of the material [P1]. The high energy of the ion beam also damages the silicon crystal structure, creating localized dangling bonds that make the surface highly susceptible to rapid re-oxidation and defect precipitation [P1], [T1]. Pre-litho and pre-deposition cleans must be chemically tuned to remove these implant-induced residues and damaged native oxides without causing excessive substrate loss [P1].

Dry Etching

During dry etching of contact vias or trenches, fluorocarbon-based plasma chemistries are frequently utilized [A1]. This process leaves behind a complex fluorocarbon polymer residue on the sidewalls and bottom of the etched features [A1]. The pre-litho clean must efficiently strip these highly inert organic polymers using dry remote-plasmas (e [P2].g., $Ar/He$ or Siconi™) or specialized wet solvents to prepare the surface for subsequent lithography or metal deposition [P2], [A1].

Thin Film Deposition and Epitaxy

The quality of subsequent deposition steps, such as atomic layer deposition (ALD) for high-k gate dielectrics or chemical vapor deposition (CVD) for epitaxial SiGe bases, is entirely dependent on the pre-clean quality [P3], [P4], [A1]. Any residual native oxide or carbon contamination acts as a defect nucleation site, leading to grain boundaries, dislocations, and film thickness non-uniformities [P3]. Effective pre-cleans enable low-temperature epitaxy by removing native oxide and passivating the surface, bypassing the need for high-temperature thermal desorption steps [P3], [P4].

Thermal Treatment

Chemical pre-cleans directly dictate the thermal budget of subsequent thermal steps [P4]. For instance, modifying the RCA clean sequence to end with an extended SC2 soak significantly reduces micro-roughness, enabling the subsequent thermal cleaning step in molecular beam epitaxy or rapid thermal annealing systems to be executed at significantly lower temperatures [P4]. This is highly beneficial for preserving sharp dopant profiles and preventing thermal relaxation of strained layers [P3], [P4].

Future Outlook

As the semiconductor industry transitions from FinFETs to gate-all-around (GAA) nanosheets and complementary FETs (CFETs), pre-clean technology faces unprecedented challenges [A2]. The GAA nanosheet architecture requires the selective lateral etching of sacrificial SiGe layers to release the silicon nanosheets, leaving behind ultra-narrow, horizontal, suspended channels [A1]. Cleaning these incredibly complex internal geometries is impossible with conventional wet chemistry due to fluid transport and capillary force limits (Engineering Practice).

To address this, the industry is transitioning toward atomic layer etching (ALE) as the ultimate dry pre-clean solution (Engineering Practice). ALE utilizes self-limiting chemical reactions to remove material monolayer-by-monolayer, ensuring atomic-scale precision, perfect selectivity, and zero physical damage (Engineering Practice).

Additionally, the absolute intolerance for Q-time re-oxidation has driven the adoption of in-situ vacuum cluster tools [A1], [A2]. In these clusters, the dry cleaning module, the surface passivation chamber, and the subsequent ALD or epitaxial deposition tools are physically integrated under a continuous, high-vacuum environment [A1], [A2]. By preventing the wafer from ever being exposed to cleanroom air between cleaning and deposition, process engineers can completely eliminate native oxide regrowth, carbon contamination, and AMC adsorption, securing the physical and electrical integrity of future sub-2nm device nodes [A1], [A2].