Technical Blog
Deep dive into the physics and integration logic of semiconductor manufacturing
EKC Post-Etch Residue Removal: Principles, Mechanisms, and Advanced Node Integration in Semiconductor Manufacturing
In semiconductor manufacturing, every plasma etch step that defines a pattern also leaves behind unwanted byproducts on the wafer surface.
Equivalent Oxide Thickness (EOT): Principles, Physics, and Advanced Node Integration
Equivalent oxide thickness (EOT) is one of the most fundamental metrics in advanced semiconductor manufacturing.
Etch Stop Layer (ESL) in Semiconductor Manufacturing: Principles, Physics, and Integration Logic
An etch stop layer (ESL) is a thin, selectively etch-resistant film deposited within a semiconductor device stack to terminate etching processes at precisely defined material…
Etch Rate: Removal, Selectivity, and Uniformity
Etch rate measures removal of a specified material over time. Learn why selectivity, location and feature shape change how the number should be read, then locate two STI etches in a public Flow.
Fin Height Adjustment in Semiconductor Manufacturing: Physical Principles, Process Mechanisms, and Advanced Node Integration
Fin height adjustment is a critical semiconductor process step that controls the vertical dimension of silicon fins in Fin Field-Effect Transistor (FinFET) devices.
Gate Oxidation (GOX): Physical Principles, Mechanisms, and Process Evolution in Semiconductor Manufacturing
Gate oxidation (GOX) is the thermal process of growing a thin, high-quality silicon dioxide (SiO₂) layer on a silicon substrate to serve as the gate dielectric in a…
HKMG Explained: High-k Dielectrics, Metal Gates and EOT
Separate dielectric capacitance, polysilicon depletion and effective work function.
Interlayer Dielectric (ILD) in Semiconductor Manufacturing: Physical Principles, Integration Logic, and Advanced Node Evolution
The interlayer dielectric (ILD) is one of the most foundational thin films in integrated circuit manufacturing.
Semiconductor Interfaces: Physical Principles, Charge Mechanisms, and Integration Challenges in Advanced CMOS
In semiconductor manufacturing, an interface is the atomically thin boundary region where two dissimilar materials meet — most famously the silicon/silicon dioxide (Si/SiO₂)…
Low Energy Contact (LEC) in Semiconductor Manufacturing: Physics, Process Principles, and Advanced Node Evolution
As CMOS technology scales deeper into the nanometer regime, the resistance associated with the interface between metal interconnects and semiconductor source/drain regions—known…
LPCVD Explained: Transport, Surface Reaction and Coverage
Distinguish transport, surface reaction and coverage when interpreting LPCVD.
LSA: Transient Heating, Activation and Thermal Integration
Laser spike anneal (LSA) is an advanced thermal processing technique that uses focused, high-intensity laser energy to rapidly heat the near-surface region of a semiconductor…