Equivalent Oxide Thickness (EOT): The Gate Dielectric Metric That Defines Modern CMOS Scaling

Introduction

Equivalent oxide thickness (EOT) is one of the most fundamental metrics in advanced semiconductor manufacturing [T1]. At its core, EOT represents the thickness that a layer of silicon dioxide (SiO₂) would need to have in order to produce the same gate capacitance as an actual dielectric stack of a different material at its actual physical thickness [P2]. In other words, EOT translates the electrical performance of any high-permittivity (high-κ) gate dielectric into the familiar language of SiO₂, which served as the gate oxide for decades [T1].

The concept became critically important because, as MOSFET dimensions shrank generation after generation, gate oxide thickness had to scale proportionally to maintain electrostatic control over the channel and to suppress short-channel effects such as threshold voltage roll-off [T1]. However, once SiO₂ physical thickness approached the sub-2-nm regime, direct quantum-mechanical tunneling through the oxide caused leakage current to rise exponentially, leading to unacceptable static power dissipation [P3]. The industry needed a way to keep increasing gate capacitance — and thus drive current — without indefinitely thinning SiO₂ [T1]. The solution was to adopt dielectric materials with higher permittivity, allowing a physically thicker film to deliver the same capacitance as a much thinner SiO₂ layer [P2]. EOT became the universal figure of merit to compare these new stacks against the SiO₂ baseline (Engineering Practice).

Today, even though SiO₂ is no longer the primary gate dielectric in advanced microprocessors, engineers still gauge gate capacitance strength using EOT [P3]. Whether dealing with planar MOSFETs, FinFETs, gate-all-around (GAA) transistors, or three-dimensional NAND flash memory cells, EOT remains the central parameter that links dielectric material properties, physical thickness, and device electrical performance [P2][A1][A2].

Physics & Mechanism

Capacitance and the Origin of EOT

The gate-to-channel capacitance of a MOS structure is given by the parallel-plate capacitor formula:

$$C = \frac{\varepsilon_0 \kappa S}{t}$$

where $\varepsilon_0$ is the permittivity of free space, $\kappa$ is the relative dielectric constant of the insulator, $S$ is the gate area, and $t$ is the physical thickness of the dielectric [P2]. For SiO₂, $\kappa$ is approximately 3.9 (Engineering Practice). If a high-κ material replaces SiO₂, a thicker physical layer can yield the same capacitance density [P1]. The equivalent oxide thickness is then defined as:

$$\text{EOT} = \frac{3.9}{\kappa_{\text{high-}k}} \times t_{\text{high-}k}$$

This equation encapsulates the central idea: a high-κ dielectric with a given physical thickness $t_{\text{high-}k}$ produces the same capacitance as an SiO₂ layer of thickness EOT [P2][P3]. For example, HfO₂ with a relative permittivity of roughly 24 can be six times thicker than SiO₂ while delivering the same Cox, thereby presenting a much wider tunneling barrier and orders-of-magnitude lower leakage [T1].

Quantum Tunneling and the Leakage Constraint

The reason EOT matters so deeply is rooted in quantum mechanics [T1]. As the physical oxide thickness shrinks, electrons can tunnel directly through the barrier [T1]. The gate leakage current density follows an exponential dependence on physical thickness and barrier height [P2]:

$$J_g = \frac{A}{T_{ox}^2} \exp\left{-2T_{ox}\sqrt{\frac{2m^* q}{\hbar^2}\left(\Phi_B - \frac{V_{ox}}{2}\right)}\right}$$

Here, $T_{ox}$ is the physical dielectric thickness, $m^*$ is the carrier effective mass in the dielectric, $\Phi_B$ is the barrier height, and $V_{ox}$ is the voltage drop across the dielectric [P2]. This equation reveals two critical levers: increasing physical thickness suppresses leakage exponentially, and increasing the barrier height (conduction-band offset) also reduces tunneling [T1]. High-κ dielectrics allow engineers to increase $T_{ox}$ while keeping EOT — and thus Cox — constant, simultaneously addressing both levers [T1].

Band Alignment and Interface Physics

The electrical behavior of MOS capacitors is governed jointly by the Poisson equation and quantum tunneling theory [P1]. High-κ dielectrics achieve smaller EOT at the same physical thickness by increasing the gate dielectric constant; however, interface state density and band alignment directly affect carrier transport [P1]. Materials such as HfO₂ have high permittivity but may suffer from lattice mismatch with the substrate and high interface defect density, which create oxide charges and trap-assisted tunneling paths [P1]. Introducing an interfacial buffer layer — such as Al₂O₃ between HfO₂ and III–V substrates — can improve chemical bonding, reduce interface state density, and increase the conduction-band offset, thereby suppressing thermionic emission and quantum tunneling simultaneously [P1].

The Electrical Oxide Thickness Concept

In practice, the effective gate capacitance is not determined by the dielectric alone [T1]. Inversion charge resides at a finite depth below the silicon surface (the charge-layer thickness, Tinv), and polysilicon gates exhibit a depletion width (Wdpoly) under inversion bias [T2]. These add series capacitances that reduce the overall gate capacitance [T1]. The electrical oxide thickness, Toxe, captures all three contributions:

$$T_{oxe} = T_{ox} + \beta \cdot T_{inv} + \beta \cdot W_{dpoly}$$

where $\beta$ is the ratio of silicon permittivity to oxide permittivity, translating Tinv and Wdpoly into equivalent oxide thickness terms [T2]. This is why replacing polysilicon gates with metal gates — which have no depletion region — is essential for minimizing Toxe and maximizing gate control at advanced nodes [T1][P2].

Process Principles

Dielectric Constant and Physical Thickness Trade-Off

The most direct process lever for EOT is the dielectric constant of the deposited material [T3]. Increasing κ allows a greater physical thickness for the same EOT, which exponentially suppresses tunneling leakage [P2]. However, high-κ materials introduce their own challenges: chemical reactions with the silicon substrate, lower surface mobility compared to the Si–SiO₂ system, and higher oxide charge [T1]. The standard integration approach is to insert a thin SiO₂ (or SiON) interfacial layer between the silicon substrate and the high-κ dielectric, preserving the superior interface quality of the Si–SiO₂ system while the high-κ layer provides the capacitance [T1]. This interfacial layer itself contributes to EOT, creating an inherent trade-off between interface quality and minimum achievable EOT (Engineering Practice).

Laminated and Bilayer Dielectric Engineering

When using laminated or bilayer dielectric stacks, the ratio of high-κ to interfacial layer thickness directly modulates the effective dielectric constant and EOT [P1]. As the fraction of the lower-κ interfacial layer (such as Al₂O₃) increases while total physical thickness is held constant, the overall effective dielectric constant decreases, EOT increases, and the electric field intensity across the stack decreases for a given gate bias [P1]. This reduces leakage but degrades gate control ability — a fundamental trade-off [P1]. Process engineers must therefore optimize the thickness ratio to balance leakage suppression against capacitance requirements [P1].

Deposition Method and Interface Quality

The deposition method strongly influences interface quality and thus the effective EOT [P2]. Deposited oxides historically had poorer interface electrical properties than thermally grown oxides, because thermal oxidation creates new SiO₂ at the Si/SiO₂ interface with near-ideal bonding [T3]. For gate dielectrics and other critical oxides, thermal oxides are preferred; deposited oxides can be annealed or supplemented with a thin underlying thermal oxide to approach thermal-oxide interface quality [T3]. Atomic layer deposition (ALD) has become the dominant technique for high-κ dielectric deposition because its surface-limited, self-terminating chemisorption mechanism ensures atomic-scale thickness control and excellent conformality on three-dimensional channel structures such as FinFETs and GAA devices [P2].

Gate Material and Work Function Engineering

The choice of gate material also affects the effective electrical thickness [T1]. Metal gates eliminate the polysilicon depletion contribution to Toxe, directly reducing the electrical oxide thickness [T1]. Furthermore, the effective work function (EWF) of metal gates is not simply the bulk material work function but is jointly determined by Fermi-level pinning, interface dipoles, and chemical composition at the metal/high-κ interface [P2]. By tuning ALD precursors, metal composition, and thermal treatments, engineers can modify interface state density and dipole strength, enabling precise threshold voltage control without changing the dielectric EOT [P2].

Interfacial Layer Scaling

The interfacial SiO₂ layer between silicon and the high-κ dielectric is often the dominant contributor to EOT in advanced stacks [P1]. Reducing its thickness lowers EOT but risks degrading interface quality and increasing leakage [T1]. Advanced techniques such as oxide densification, nitridation, and remote plasma treatments can improve the quality and effective permittivity of this interfacial layer, allowing thinner layers without sacrificing interface state density [T3]. This interfacial layer engineering is closely related to dual gate oxide strategies used in mixed-voltage domains [P2].

Challenges & Failure Modes

Leakage Current and Tunneling Breakdown

The most prominent failure mode is excessive gate leakage current [T1]. When EOT is pushed too low — either by reducing physical thickness or by increasing κ at the expense of barrier height — direct tunneling dominates and leakage rises exponentially [P2]. In HfO₂/InAlAs systems, lattice mismatch and high interface defect density create oxide charges and trap-assisted tunneling paths, leading to leakage current that can exceed acceptable limits under high bias [P1]. The laminated HfO₂–Al₂O₃ approach demonstrates that while increasing the Al₂O₃ fraction reduces leakage by raising the conduction-band offset, it simultaneously increases EOT and degrades gate control — a direct manifestation of the EOT–leakage trade-off [P1].

Interface Traps and C–V Hysteresis

Interface state density at the dielectric/semiconductor interface causes capacitance–voltage (C–V) stretch-out, hysteresis, and Fermi-level pinning [P1][P3]. III–V semiconductors such as InAlAs and germanium are particularly sensitive: thermodynamically unstable oxides and high densities of dangling bonds lead to high interface state densities that degrade subthreshold characteristics and threshold voltage stability [P3]. In the HfO₂/Al₂O₃ laminated system, the Al₂O₃ interfacial buffer layer reduces effective oxide charge density from levels above 1.8×10¹² cm⁻² to as low as 0.78×10¹² cm⁻², demonstrating that interface engineering is essential for achieving low EOT without catastrophic leakage [P1].

Oxide Breakdown and Reliability

If the dielectric is too thin, the electric field can cause destructive breakdown — a catastrophic failure mode [T1]. Even below the breakdown threshold, long-term operation at high field, especially at elevated chip operating temperatures, breaks weaker chemical bonds at the Si–SiO₂ interface, creating oxide charge and causing Vt shift over the device lifetime [T1]. These reliability concerns set a practical floor on how aggressively EOT can be scaled for a given material system (Engineering Practice).

Three-Dimensional Structure Challenges

In FinFET and GAA architectures, achieving uniform dielectric deposition on vertical and horizontal surfaces is critical [P2]. Conventional physical vapor deposition (PVD) suffers from insufficient conformality in three-dimensional structures, leading to non-uniform EOT across the channel and localized thin spots that become leakage hotspots [P2]. ALD addresses this through its surface-reaction-limited mechanism, but process parameters such as precursor exposure time, temperature, and purge duration must be carefully controlled to ensure self-terminating saturation on all surfaces [P2].

Memory Device-Specific Failure Modes

In three-dimensional NAND flash memory, the blocking layer and tunnel layer each have distinct EOT requirements [A1]. The blocking layer EOT must be thicker than the tunnel layer EOT to prevent back-tunneling of stored charge while allowing programming erase operations [A1][A2]. Non-uniform thickness or defects in either layer cause gate dielectric leakage or breakdown, leading to data retention failures [A2]. The interlayer dielectric between electrode layers in these stacked structures must also maintain precise thickness control to ensure consistent electrical film thickness across hundreds of stacked layers [A2].

Technology Node Evolution

The 28nm Era and the SiO₂ Limit

At the 28nm node, the industry was approaching the fundamental limits of SiO₂ scaling [T1]. Gate oxide thickness had been reduced from roughly 300nm at the 10µm technology node to only about 1.2nm at the 65nm node, scaling roughly in proportion to linewidth [T1]. By 28nm, SiO₂ or SiON gate oxides were near the tunneling leakage threshold, and nitrogen incorporation was used to modestly reduce leakage [T1]. The 28nm planar flow represents one of the last nodes where SiO₂-based gate dielectrics were viable without high-κ integration [T1].

14nm and the High-κ/Metal Gate Transition

At 14nm, FinFET architectures became mainstream, and high-κ/metal gate (HKMG) technology was essential [P2]. HfO₂-based dielectrics with κ values around 24 replaced SiO₂ as the primary gate oxide, allowing physical thickness several times larger than the equivalent SiO₂ thickness while maintaining the same Cox [T1]. ALD became indispensable for depositing both the high-κ dielectric and the metal gate on three-dimensional fin structures, ensuring conformal coverage and atomic-scale thickness control [P2]. The 14nm FinFET flow exemplifies this transition [T1]. Metal gates — often titanium nitride or tantalum nitride based — eliminated polysilicon depletion, reducing Toxe and enabling tighter EOT scaling [P2][T1].

7nm and Sub-7nm: EOT Scaling Limits

At 7nm and beyond, EOT scaling becomes increasingly difficult (Engineering Practice). The interfacial SiO₂ layer between silicon and HfO₂ now dominates the total EOT budget, and further reduction risks degrading interface quality [P3]. Research targets from the ITRS called for manufacturable EOT values below 1nm for Ge and III–V devices, requiring materials with permittivity around 20 to achieve physical thickness above 4nm — pushing the boundaries of what current material systems can deliver [P3]. The 7nm FinFET flow illustrates the complexity of gate stack engineering at this node [P2]. For emerging channel materials like germanium, the unstable GeOₓ interface and high interface state density create additional barriers to achieving aggressive EOT targets [P3].

Beyond 7nm: GAA and New Channel Materials

Looking beyond 7nm, gate-all-around (GAA) architectures further tighten EOT requirements because the gate must wrap entirely around the nanosheet or nanowire channel, demanding perfect conformality from the dielectric deposition [P2]. New channel materials — germanium for PMOS, III–V compounds for NMOS — offer higher mobility but introduce severe interface challenges that complicate EOT scaling [P3]. Laminated dielectric approaches, such as HfO₂–Al₂O₃ stacks, demonstrate that band-structure engineering can partially compensate for interface quality limitations, but the EOT penalty of lower-κ interfacial layers remains a fundamental constraint [P1].

Related Processes

Gate Dielectric Deposition and Oxide Growth

EOT is intimately connected to the gate dielectric formation process [P2]. Thermal oxidation of silicon provides the highest-quality SiO₂ interface but is limited to SiO₂ growth and cannot produce high-κ films [T3]. For plasma enhanced oxide and other deposited oxides, interface quality is generally inferior, requiring annealing or supplemental thermal oxide growth to approach thermal-oxide electrical characteristics [T3]. ALD is the method of choice for high-κ deposition because it enables layer-by-layer growth with sub-angstrom thickness precision [P2].

Metal Gate Deposition

Metal gate deposition is tightly coupled with EOT engineering because the gate material determines both the depletion contribution to Toxe and the effective work function that sets Vt [P2]. ALD metal gates — using titanium nitride or similar compounds — provide the conformality and work function tunability needed for advanced nodes [P2]. The interface between the metal gate and the high-κ dielectric creates dipoles that shift the effective work function, meaning that metal gate process parameters directly influence the electrical behavior of the entire gate stack [P2].

Channel Engineering and Strain Integration

EOT interacts with channel engineering through the charge-layer thickness Tinv, which depends on carrier effective mass and substrate doping [T1][T2]. Strained silicon and alternative channel materials modify the band structure and effective mass, affecting Tinv and thus the total electrical oxide thickness Toxe [T3]. For germanium channels, the high hole mobility reduces scattering and can improve inversion charge response, but the unstable oxide interface complicates dielectric integration [P3].

Memory Cell Stack Engineering

In NAND flash and other charge-trapping memory devices, EOT plays a role in both the tunnel layer and the blocking layer [A1]. The tunnel layer EOT must be thin enough to allow Fowler-Nordheim tunneling during program/erase operations, while the blocking layer EOT must be thick enough to prevent charge loss [A1][A2]. The ratio of these two EOTs determines the memory cell's programming window and retention characteristics [A2]. Silicon nitride is often used in these stacks, and its permittivity directly influences the blocking layer EOT — connecting silicon nitride process engineering to memory device performance [A2].

Future Outlook

The future of EOT scaling lies at the intersection of materials science, interface engineering, and device architecture [P2]. Several emerging directions are shaping research:

Higher-κ dielectrics: Materials such as HfO₂-ZrO₂ laminates, perovskite oxides, and rare-earth oxides promise permittivity values well above 30, potentially enabling sub-nanometer EOT with physically thicker layers [P1]. However, stability, crystallization behavior, and interface compatibility remain active research challenges (Engineering Practice).

Interfacial layer engineering: Replacing the SiO₂ interfacial layer with higher-κ alternatives — such as La₂O₃, Y₂O₃, or Al₂O₃ with dipole engineering — can reduce the interfacial contribution to EOT without sacrificing interface quality [P1]. Dipole layers created by capping the high-κ with rare-earth oxides can shift the effective work function and compensate for the EOT penalty of the interfacial layer [P2].

New channel material integration: Germanium and III–V channels offer mobility advantages but require fundamentally different dielectric interfaces [P3]. Laminated approaches, as demonstrated by the HfO₂–Al₂O₃ system on InAlAs, show that band-structure engineering can enable low-leakage gate stacks on these materials, though EOT penalties remain [P1][P3].

Ferroelectric and negative capacitance dielectrics: Emerging ferroelectric materials such as HfO₂-ZrO₂ in their orthorhombic phase can create negative capacitance effects, effectively amplifying gate voltage and allowing steeper subthreshold swings [T2]. This could relax the EOT scaling requirement by improving gate efficiency through a different physical mechanism [T1].

Three-dimensional architecture challenges: As GAA and 3D stacking architectures mature, dielectric deposition must achieve perfect conformality on increasingly complex geometries [P2]. ALD will remain the enabling technology, but precursor chemistry and process windows must evolve to meet the demands of multi-stacked nanosheet channels [P2][A1].

The relentless drive to reduce EOT while maintaining low leakage and high reliability will continue to define the frontier of semiconductor process engineering for the foreseeable future [T1].