Demystifying Over Polishing in Semiconductor Manufacturing: Mechanisms, Challenges, and Advanced Node Integration

Introduction

In modern semiconductor manufacturing, achieving global planarization across a silicon wafer is a fundamental prerequisite for high-resolution lithography and multi-level interconnect integration. This spatial uniformity is primarily accomplished through chemical mechanical planarization (CMP), a process that simultaneously leverages chemical action and mechanical abrasion to remove excess material.

However, due to inherent incoming film non-uniformity, wafer-level variations, and localized pattern density differences, a timed polishing step rarely clears the target film uniformly across the entire wafer surface. An overpolish step is performed to ensure that all the excess metal is removed from on top of the dielectric layer [T1]. Over polishing is defined as the continued application of the CMP process after the nominal point of clearance has been reached at the thinnest or fastest-polishing regions of the wafer. While indispensable for preventing electrical shorts and ensuring high yield, over polishing introduces structural and electrical challenges, including localized material recession, defect generation, and dielectric degradation.

Physics & Mechanism

The Tribochemical Synergy

The physical and chemical removal mechanisms during over polishing rely on a coupled synergistic interaction between chemical passivation and mechanical shear stress. In a typical metallic CMP process, such as those utilized in copper dual damascene metallization, the slurry contains an oxidizer, a complexing agent, and a passivation inhibitor.

During the initial polishing phase, the oxidizer—typically hydrogen peroxide (H2O2)—reacts with the metal surface to form a native oxide or hydroxide passivation layer. The passivation layer suppresses isotropic chemical etching in low-lying recessed areas, preventing uncontrolled metal dissolution. Simultaneously, the mechanical action of the polishing pad and abrasive particles exerts localized shear stress on protruding topographies, preferentially removing the weakened passivation layer and exposing fresh metal to further oxidation and removal.

Pad Mechanics and Elastic Deformation

When the process transitions into the over polishing phase, the bulk metal film is cleared, exposing the underlying barrier or dielectric stopping layer. Ideally, the polishing process should halt abruptly at this interface. However, because polishing pads possess a finite elasticity, the pad material deforms under the applied downforce.

As the pad sweeps across the wafer, its asperities bend and compress, enabling the pad to penetrate into trenches filled with softer metals. In classical wear modeling, Preston's equation relates the material removal rate linearly to the applied down pressure and relative velocity . In recessed structures, the elastic deformation of the pad transfers a portion of the downforce directly to the exposed trench metal, accelerating removal within the trenches and generating a concave profile known as dishing.

High-Selectivity Slurry Kinetics

In applications like shallow trench isolation (STI) CMP, high-selectivity slurries (HSS) containing ceria (CeO2) abrasives are employed to stop polishing on a silicon nitride (Si3N4) liner. The chemical mechanism of ceria-based HSS depends on the formation of temporary Ce-O-Si bonds at the silica (SiO2) surface, which significantly lowers the mechanical energy barrier required to shear away the oxide.

Conversely, polymeric or chemical additives are engineered to selectively adsorb onto the silicon nitride surface, forming a dense barrier that blocks abrasive contact and suppresses chemical reactions. During the over polish phase, this adsorption layer prevents nitride erosion, widening the process margin. However, prolonged over polishing can eventually deplete or disrupt this dynamic inhibition layer, leading to hot-spot erosion and localized trench oxide loss. Experimental studies on patterned wafers show that the copper-to-liner selectivity is a function of pattern density, including line width and spacing .

Process Principles

The performance and control of the over polishing process are governed by several key process parameters. Modulating these parameters allows process engineers to optimize the overpolish window without inducing excessive planarization loss.

Applied Downforce and Pad Properties

• Downforce Impact: Increasing the downforce applied to the wafer carrier increases contact stress at the pad-wafer interface. While this accelerates the overall removal rate, it also intensifies pad deformation, increasing dishing and erosion during the overpolish phase.
• Pad Rigidity: The elastic modulus of the polishing pad determines its resistance to bending. A rigid pad resists deformation into trenches, suppressing dishing in wide features. However, rigid pads are less compliant to wafer-scale macro-topography, potentially worsening within-wafer (WIW) and within-die (WID) uniformity. Soft pads improve macro-uniformity but worsen localized dishing.

Slurry Formulation and Inhibitor Dynamics

• Oxidizer and Complexing Agent Concentration: High concentrations of oxidizer accelerate the passivation rate, but if mechanical removal during overpolish cannot keep pace, a highly passive system can lead to non-uniform clearance. Conversely, insufficient passivation allows chemical components to isotropically etch recessed features, accelerating dishing and pitting.
• Inhibitor and Surfactant Adsorption: Adding organic inhibitors (e.g., azoles for copper or cationic surfactants for tungsten/molybdenum) is critical to protect metal features during overpolish. A higher concentration of these inhibitors increases passivation strength in the trenches, reducing the dishing rate during over polishing. However, excessive inhibitor concentrations can lower the overall removal rate and cause residue defects.

Relative Velocity and Polish Time

• Relative Velocity: Higher platen and carrier rotational speeds increase relative velocity, raising the mechanical removal rate. This reduces nominal clearing time, but if overpolish time is kept constant, higher velocities increase dishing and erosion due to increased mechanical energy delivered to recessed features.
• Overpolish Ratio: Typically defined as a percentage of the nominal polish time, the overpolish ratio must be carefully balanced. A low overpolish ratio risks leaving metal or barrier residues, whereas a high overpolish ratio continuously worsens planarity, thinning dielectric features and compromising electrical performance.

Challenges & Failure Modes

During over polishing, several distinct physical and structural failure modes can occur, impacting yield and reliability.

Dishing

Dishing occurs when the metal inside a trench is polished faster than the surrounding dielectric barrier, leading to a concave surface topography. This effect is non-linear and is significantly more pronounced in wide metal lines and structures with low pattern densities. The primary physical cause of dishing is pad deflection into the trench, which allows abrasive particles to continue removing metal even after the adjacent dielectric field has been cleared. Dishing reduces the effective cross-sectional area of the metal interconnect, leading to elevated sheet resistance and localized electromigration risks.

Erosion

Erosion is characterized by the collective thinning of both the metal lines and the intervening dielectric space in high-density pattern regions. Unlike dishing, which is a localized feature-level phenomenon, erosion occurs over larger pattern arrays where high feature density reduces effective mechanical resistance. The polishing pad exerts higher localized pressure on these compliant regions, causing accelerated removal of both metal and dielectric barriers. This thins the interlevel dielectric, leading to increased parasitic capacitance and breakdown voltage degradation.

Scratch Defects and Particle Agglomeration

Prolonged over polishing increases cumulative mechanical stress on the wafer surface, generating physical defectivity. In ceria-based STI polishing, pH environment and surfactant concentrations can shift dynamically during over polishing. This chemical drift can destabilize slurry suspension, causing sub-micron abrasive particles to agglomerate into larger aggregates. Under continuous shear and downforce, these large particles scratch active surfaces, creating deep micro-scratches that damage gate oxide integrity.

Delamination of Low-k Dielectrics

In advanced back-end-of-line (BEOL) interconnects, mechanically fragile low-k dielectric materials are utilized to minimize parasitic capacitance. These materials have higher porosity and lower cohesive strength compared to thermal oxides. During extended over polishing, sustained lateral shear forces and friction can exceed the interfacial adhesion strength between the low-k dielectric and the barrier metal layer, resulting in film delamination and cracking.

Technology Node Evolution

The management of over polishing has undergone significant transformation as the semiconductor industry transitioned from planar transistors to complex three-dimensional architectures.

Technology Node	Primary CMP Challenge	Over Polish Control Strategy	Key Materials Introduced
28nm (Planar)	Dual Damascene planarization and gate-last integration	Optical and motor-current end-point detection (EPD) to minimize overpolish time	Acidic alumina slurries, first-generation low-k dielectrics
14nm (FinFET)	Fin height uniformity and complex replacement metal gate (RMG) planarization	High-selectivity slurries with chemical inhibitors to self-stop on thin stopping layers	Cobalt liners, high-selectivity ceria slurries
7nm & Beyond (FinFET / GAA)	Extreme topography, ultra-thin barrier layers, and high-aspect-ratio contacts	Multi-step selective CMP with specialized molecular inhibitors to protect molybdenum/ruthenium	Ruthenium, Molybdenum, ultra-low-k (ULK) dielectrics

At the planar 28nm node, copper dishing and erosion were managed primarily through pad conditioning and optimizing polyurethane pad rigidity. The introduction of the replacement metal gate process at the 14nm node demanded precise planarization of gate materials without eroding source/drain contacts, requiring narrow overpolish windows. At 7nm and beyond, integration of alternative metals like ruthenium and molybdenum has necessitated advanced multi-step CMP schemes. These schemes utilize specialized molecular inhibitors to selectively adsorb onto specific metals, chemically stopping over polishing at molecular interfaces.

Related Processes

The consequences and requirements of over polishing are tightly integrated with upstream and downstream process steps.

Upstream, film deposition profiles—whether from atomic layer deposition or electrochemical plating—establish starting topography. Non-uniformities in deposition require longer over polishing times to ensure complete clearance across the wafer surface.

Downstream, planarity achieved after over polishing directly impacts extreme ultraviolet (EUV) lithography, where depth of focus is limited. Residual topography from overpolish-induced dishing or erosion can lead to pattern distortion during exposure. Furthermore, over polishing is coupled with dry etching, as variations in post-CMP dielectric thickness alter landing depth and profile of subsequent via etches.

Future Outlook

As the semiconductor industry advances toward nanosheet gate-all-around (GAA) transistors and back-side power delivery networks, over polishing control must reach atomic-scale precision. Traditional chemical-mechanical mechanisms are being augmented by electrochemical-mechanical planarization, which uses localized potential control to fine-tune passivation layer dissolution during over polish.

Additionally, the industry is exploring integration of atomic layer etching concepts within the CMP chamber to enable selective, damage-free removal of residues, bypassing mechanical stresses that cause dishing, erosion, and delamination in fragile multi-layer systems. Real-time optical monitoring and automated process control are also deployed to dynamically adjust downforce profiles across wafer zones during overpolish, ensuring atomic flatness across 300mm substrates.