Introduction
In modern semiconductor manufacturing, achieving global planarization across a silicon wafer is a fundamental prerequisite for high-resolution lithography and multi-level interconnect integration . This spatial uniformity is primarily accomplished through chemical mechanical planarization (CMP), a process that simultaneously leverages chemical action and mechanical abrasion to remove excess material . However, due to inherent incoming film non-uniformity, wafer-level variations, and localized pattern density differences, a timed polishing step rarely clears the target film uniformly across the entire wafer surface .
To guarantee that no conductive or dielectric residues remain to cause device failures, engineers must implement a planned phase known as over polishing (often termed as overpolish) . Over polishing is defined as the continued application of the CMP process after the nominal point of clearance has been reached at the thinnest or fastest-polishing regions of the wafer . While indispensable for preventing electrical shorts and ensuring high yield, over polishing introduces significant structural and electrical challenges, including localized material recession, defect generation, and dielectric degradation . Understanding the fundamental physical and chemical mechanisms of over polishing is crucial for design and process integration engineers working on advanced technology nodes .
Physics & Mechanism
The Tribochemical Synergy
The physical and chemical removal mechanisms during over polishing rely on a highly coupled synergistic interaction between chemical passivation and mechanical shear stress , . In a typical metallic CMP process, such as those utilized in copper dual damascene metallization, the slurry contains an oxidizer, a complexing agent, and a passivation inhibitor , .
During the initial polishing phase, the oxidizer—typically hydrogen peroxide ($H_2O_2$)—reacts with the metal surface to form a native oxide or hydroxide passivation layer , . The passivation layer suppresses isotropic chemical etching in low-lying recessed areas, preventing uncontrolled metal dissolution . Simultaneously, the mechanical action of the polishing pad and abrasive particles exerts localized shear stress on protruding topographies, preferentially removing the weakened passivation layer and exposing fresh metal to further oxidation and removal , , .
Pad Mechanics and Elastic Deformation
When the process transitions into the over polishing phase, the bulk metal film is cleared, exposing the underlying barrier or dielectric stopping layer , . Ideally, the polishing process should halt abruptly at this interface . However, because polishing pads possess a finite elasticity, the pad material deforms under the applied downforce .
As the pad sweeps across the wafer, its asperities bend and compress, enabling the pad to penetrate into the trenches filled with softer metals , . According to Preston's equation, the material removal rate is proportional to the local contact pressure and the relative velocity of the polishing interface . In recessed structures, the elastic deformation of the pad transfers a portion of the downforce directly to the exposed trench metal, accelerating removal within the trenches and generating a concave profile known as dishing , .
High-Selectivity Slurry Kinetics
In applications like shallow trench isolation (STI) CMP, high-selectivity slurries (HSS) containing ceria ($CeO_2$) abrasives are employed to stop polishing precisely on a silicon nitride ($Si_3N_4$) liner , . The chemical mechanism of ceria-based HSS depends on the formation of temporary Ce-O-Si bonds at the silica ($SiO_2$) surface, which significantly lowers the mechanical energy barrier required to shear away the oxide .
Conversely, polymeric or chemical additives (such as anionic or cationic surfactants) are engineered to selectively adsorb onto the silicon nitride surface, forming a dense barrier that blocks abrasive contact and suppresses chemical reactions , , . During the over polish phase, this adsorption layer prevents nitride erosion, widening the process margin; however, prolonged over polishing can eventually deplete or disrupt this dynamic inhibition layer, leading to hot-spot erosion and localized trench oxide loss , .
Process Principles
The performance and control of the over polishing process are governed by the directional interaction of several key process parameters . Modulating these parameters allows process engineers to optimize the overpolish window without inducing excessive planarization loss .
Applied Downforce and Pad Properties
- Downforce Directional Impact: Increasing the downforce applied to the wafer carrier directly increases the contact stress at the pad-wafer interface , . While this accelerates the overall removal rate, it also intensifies pad deformation, resulting in a dramatic increase in the rate of dishing and erosion during the overpolish phase , .
- Pad Rigidity: The elastic modulus of the polishing pad determines its resistance to bending . A highly rigid pad resists deformation into trenches, significantly suppressing dishing in wide features . However, highly rigid pads are less compliant to wafer-scale macro-topography, potentially worsening within-wafer (WIW) and within-die (WID) uniformity . Soft pads improve macro-uniformity but worsen localized dishing .
Slurry Formulation and Inhibitor Dynamics
- Oxidizer and Complexing Agent Concentration: High concentrations of oxidizer accelerate the passivation rate, but if the mechanical removal during overpolish cannot keep pace, a highly passive system can lead to non-uniform clearance , . Conversely, insufficient passivation allows the chemical components to isotropically etch the recessed features, accelerating dishing and pitting .
- Inhibitor and Surfactant Adsorption: The addition of organic inhibitors (e (Engineering Practice).g., azoles for copper or cationic surfactants for tungsten/molybdenum) is critical to protect metal features during overpolish . A higher concentration of these inhibitors increases the strength of the passivation layer in the trenches, reducing the dishing rate during over polishing , . However, excessive inhibitor concentrations can lower the overall removal rate and cause residue defects (Engineering Practice).
Relative Velocity and Polish Time
- Relative Velocity: Higher platen and carrier rotational speeds increase the relative velocity, raising the mechanical removal rate , . This reduces the nominal clearing time, but if the overpolish time is kept constant, higher velocities will systematically increase dishing and erosion due to the increased mechanical energy delivered to the recessed features .
- Overpolish Ratio: Typically defined as a percentage of the nominal polish time, the overpolish ratio must be carefully balanced . A low overpolish ratio risks leaving metal or barrier residues, whereas a high overpolish ratio continuously worsens planarity, thinning dielectric features and compromising electrical performance , .
Challenges & Failure Modes
During over polishing, several distinct physical and structural failure modes can occur, which directly impact the yield and reliability of integrated circuits .
Dishing
Dishing occurs when the metal inside a trench is polished faster than the surrounding dielectric barrier, leading to a concave surface topography , . This effect is highly non-linear and is significantly more pronounced in wide metal lines and structures with low pattern densities , . The primary physical cause of dishing is pad deflection into the trench, which allows the abrasive particles to continue removing metal even after the adjacent dielectric field has been cleared , . Dishing reduces the effective cross-sectional area of the metal interconnect, leading to elevated sheet resistance, localized electromigration hot-spots, and subsequent device failure .
Erosion
Erosion is characterized by the collective thinning of both the metal lines and the intervening dielectric space in high-density pattern regions (Engineering Practice). Unlike dishing, which is a localized feature-level phenomenon, erosion occurs over larger pattern arrays where the high density of metal features reduces the effective mechanical resistance of the composite surface . The polishing pad exerts higher localized pressure on these compliant regions, causing accelerated, non-selective removal of both the metal and the dielectric barrier , . This thins the interlevel dielectric, leading to increased parasitic capacitance, breakdown voltage degradation, and planarization failure in subsequent lithography steps .
Scratch Defects and Particle Agglomeration
Prolonged over polishing increases the cumulative mechanical stress on the wafer surface, which can generate physical defectivity . In ceria-based STI polishing, the pH environment and surfactant concentrations can shift dynamically during over polishing . This chemical drift can destabilize the slurry suspension, causing sub-micron abrasive particles to agglomerate into larger, hard aggregates . Under the continuous shear and downforce of the polishing pad, these large particles scratch the active silicon nitride or silicon dioxide surfaces, creating deep micro-scratches that can damage gate oxide integrity and cause catastrophic yield loss .
Delamination of Low-k Dielectrics
In advanced back-end-of-line (BEOL) interconnects, mechanically fragile low-k dielectric materials are utilized to minimize parasitic capacitance . These materials have high porosity and lower cohesive strength compared to thermal oxides (Engineering Practice). During extended over polishing, the sustained lateral shear forces and friction can exceed the interfacial adhesion strength between the low-k dielectric and the barrier metal layer, resulting in catastrophic film delamination and cracking .
Technology Node Evolution
The management of over polishing has undergone significant transformation as the semiconductor industry transitioned from planar transistors to complex three-dimensional architectures .
| Technology Node | Primary CMP Challenge | Over Polish Control Strategy | Key Materials Introduced |
|---|---|---|---|
| 28nm (Planar) 28nm Planar Flow | Dual Damascene planarization and gate-last integration | Optical and motor-current end-point detection (EPD) to minimize overpolish time | Acidic alumina slurries, first-generation low-k dielectrics , |
| 14nm (FinFET) 14nm FinFET | Fin height uniformity and complex replacement metal gate (RMG) planarization | High-selectivity slurries with chemical inhibitors to self-stop on thin stopping layers | Cobalt liners, high-selectivity ceria slurries , , |
| 7nm & Beyond (FinFET / GAA) 7nm FinFET | Extreme topography, ultra-thin barrier layers, and high-aspect-ratio contacts | Multi-step selective CMP with specialized molecular inhibitors to protect molybdenum/ruthenium | Ruthenium, Molybdenum, ultra-low-k (ULK) dielectrics |
At the planar 28nm node, copper dishing and erosion were managed primarily through pad conditioning and optimizing the rigidity of polyurethane pads , . The introduction of the replacement metal gate process at the 14nm node demanded precise planarization of gate materials without eroding the source/drain contacts, requiring extremely narrow overpolish windows . At 7nm and beyond, the integration of alternative metals like ruthenium and molybdenum has necessitated advanced multi-step CMP schemes . These schemes utilize specialized molecular inhibitors to selectively adsorb onto specific metals, chemically stopping the over polishing process at molecular interfaces to prevent structural damage .
Related Processes
The consequences and requirements of the over polishing process are tightly integrated with both upstream and downstream process steps .
Upstream, the film deposition profiles—whether from atomic layer deposition or electrochemical plating—directly establish the starting topography (Engineering Practice). Non-uniformities in deposition require longer over polishing times to ensure complete clearance across the entire wafer surface .
Downstream, the planarity achieved after over polishing directly impacts extreme ultraviolet (EUV) lithography, where the depth of focus is extremely limited . Any residual topography from overpolish-induced dishing or erosion can lead to pattern distortion or bridging defects during subsequent exposure steps . Furthermore, over polishing is closely coupled with dry etching, as variations in the post-CMP dielectric thickness alter the landing depth and profile of subsequent via etches, potentially leading to open circuits or resistive contacts .
Future Outlook
As the semiconductor industry advances toward nanosheet gate-all-around (GAA) transistors and back-side power delivery networks, over polishing control must reach atomic-scale precision (Engineering Practice). Traditional chemical-mechanical mechanisms are being augmented by electrochemical-mechanical planarization, which uses localized potential control to fine-tune the passivation layer dissolution during the over polish phase .
Additionally, the industry is exploring the integration of atomic layer etching concepts within the CMP chamber to enable highly selective, damage-free removal of residues, completely bypassing the mechanical stresses that cause dishing, erosion, and delamination in fragile multi-layer systems . Real-time, multi-wavelength optical monitoring and artificial intelligence-driven process control are also being deployed to dynamically adjust downforce profile across the wafer zone-by-zone during the overpolish phase, ensuring atomic flatness across 300mm substrates .