Understanding Litho-Etch-Litho-Etch (LELE): Physical Principles, Process Integration, and Advanced Node Evolution

Introduction

In the continuous pursuit of scaling down silicon integrated circuit (IC) features, semiconductor manufacturing eventually encountered the fundamental physical boundaries of optical resolution [T2]. According to the Rayleigh resolution criterion, the minimum resolvable feature size is directly proportional to the exposure wavelength and inversely proportional to the numerical aperture (NA) of the projection optics [T2]. When optical lithography using immersion tools hit its theoretical scaling limit, printing dense, sub-resolution patterns with a single exposure became physically impossible due to the diffraction limit of light [P4].

To circumvent this barrier, the industry turned to double patterning technology as an elegant scaling approach to double the spatial density of patterned lines [P1, P2]. Among the early multi-patterning methodologies, litho-etch-litho-etch (LELE) emerged as a premier pitch-splitting strategy [P1, P4]. By dividing a dense layout into two sparser, interleaved subsets, LELE allows existing exposure systems to print patterns that would otherwise be blurred into a single continuous sheet of light under single-exposure conditions [P2]. This article explores the core physical mechanisms, integration challenges, and technological evolution of the LELE process [P3].

Physics & Mechanism

At its core, LELE relies on spatial frequency doubling through layout decomposition and sequential pattern transfer [P2]. The physical layout is mathematically split into two distinct masks (often designated as the target and complementary patterns) where the pitch of each mask is twice that of the final target pitch [P2, P4]. This frequency division relaxes the optical projection requirements, enabling high-contrast aerial images to form on the photoresist [P2].

The fundamental mechanical and physical sequence of the LELE process is structured as follows:

1 (Engineering Practice). First Lithography Step: A substrate is coated with a bottom anti-reflective coating (BARC) and a photoresist [P4]. The exposure tool projects the first mask pattern, transferring a latent chemical image into the resist, which is then developed to establish the first set of lines [P4, A1]. 2. First Etch Step: The developed photoresist pattern is transferred into an underlying intermediate hard mask layer using highly anisotropic dry etching [P3, T1]. This step chemically freezes the first pattern into a durable, solid-state material [A1]. 3. Resist Strip: The remaining first-level photoresist is chemically stripped, leaving behind a patterned hard mask with wide trenches [P3]. 4. Second Lithography Step: The wafer is coated with a second planarizing organic layer, BARC, and a second photoresist layer [T1]. The second exposure is aligned relative to the first hard mask features, placing the second pattern directly in the middle of the empty spaces of the first pattern [P4, A1]. 5. Second Etch Step: The second developed pattern is etched into the hard mask, combining both sets of patterns into a single, high-density composite hard mask [P3, A1]. Ultimately, this unified hard mask is used to transfer the ultra-dense features into the target layer, such as a silicon substrate or metal dielectric layer [P3].

The physical chemistry of the etching steps is governed by reactive ion etching (RIE) principles [T2, P3]. In RIE, a low-pressure discharge plasma creates highly reactive radicals and energetic ions [T2, P3]. While the chemical radicals adsorb and react on the exposed surfaces to form volatile products, the vertically accelerated ions provide directional physical sputtering that breaks surface bonds, driving a highly anisotropic, vertical etch profile [T1, T2, P3]. This combination of chemical selectivity and physical directionality is what allows the first pattern to remain structurally intact while the second pattern is introduced adjacent to it [T1, T2].

Process Principles

To successfully execute an LELE integration scheme, process parameters must be directionally balanced to prevent pattern distortion (Engineering Practice). The final critical dimension (CD) and pitch uniformity are highly sensitive to several interacting process factors:

• Overlay Alignment Accuracy: In LELE, the second lithographic step is decoupled from the first, meaning that the relative position of the second pattern depends entirely on the mechanical alignment capability of the exposure tool [P1, P4]. Any directional overlay error shifts the second pattern closer to one side of the first pattern, creating an alternating wide-and-narrow space profile [P4]. Precise control of alignment offsets is critical to prevent device performance degradation or electrical shorting (Engineering Practice).
• Etch Selectivity: During the second anisotropic etch, the chemistry must be optimized to selectively remove target materials without degrading the first hard mask pattern [T1, A1]. If the etch selectivity between the target film and the hard mask is insufficient, mask erosion occurs [T1, A1]. This directionally increases line-edge roughness (LER) and line-width roughness (LWR), ultimately leading to CD loss and structural degradation [P1, T1].
• Surface Planarization: Because the second lithography step must be patterned over the pre-existing topography of the first etched features, global and local planarization are vital [T1]. Spin-on carbon or organic planarizing layers are applied to fill the trenches, providing a flat surface that minimizes focus variation across the exposure field during the second lithographic step [T1].
• Photolithographic Exposure Dose and Focus: The energy delivered during the first and second exposure passes must be precisely balanced (Engineering Practice). Any directional mismatch in exposure dose or focus between the two passes translates directly to systematic CD differences between the first and second populations of printed features [P4].

Challenges & Failure Modes

Despite its capability to double pattern density, LELE is highly susceptible to specific physical failure modes that stem from its decoupled, multi-step nature [P1].

Overlay-Induced CD Asymmetry

Unlike self-aligned double patterning (SADP), where the spacer deposition thickness determines the spatial spacing with high physical uniformity, LELE is fundamentally limited by the placement accuracy of the exposure tool [P1, P2]. An overlay error causes the second line to physically drift toward the first, resulting in asymmetric CD and unequal spacing [P1, P4]. If the overlay error exceeds the process window, adjacent lines will physically merge, leading to catastrophic bridging failures [P4].

Line-End Shortening and Stitching Conflicts

When breaking down complex two-dimensional (2D) layout geometries into two separate masks, designers must split continuous polygons, creating "stitch" points [P2]. At these stitch boundaries, light diffraction during exposure causes the resist lines to contract, a phenomenon known as line-end shortening [P2]. During the subsequent etching steps, this shortening can prevent the split lines from overlapping correctly, resulting in electrical open-circuit failures at the stitch joints [P2].

Hard Mask Erosion and Structural Collapse

Multiple RIE steps expose the hard mask materials to repetitive physical sputtering and chemical attack [T1, T2, P3]. As the aspect ratio of the features increases, the high-energy ion bombardment can cause physical erosion or mechanical bowing of the mask sidewalls [T1]. In extreme cases, the combination of mechanical stress and reduced cross-sectional area causes the high-aspect-ratio hard mask lines to undergo mechanical collapse, ruining pattern transfer integrity [A1].

Technology Node Evolution

The implementation of LELE has adapted dynamically as scaling progressed through various industry milestones, including the transitions from planar to vertical transistor architectures (Engineering Practice).

The 28nm Node

During the manufacturing of planar devices at the 28nm Planar Flow node, standard single-exposure 193nm immersion lithography reached its physical limits for printing dense metals and gates [T2]. LELE was widely adopted as the primary solution to split the pitch of critical back-end-of-line (BEOL) metal layers, such as the metal-1 (M1) and metal-2 (M2) trenches, allowing the continuation of density scaling (Engineering Practice).

The 14nm Node

With the introduction of the fin field effect transistor (FinFET) at the 14nm FinFET node, spatial density requirements became even more rigorous [A2]. While highly periodic structures like the Fin array were transitioned to spacer-based SADP due to its superior overlay tolerance, LELE remained essential for patterning the more random, non-periodic features, such as contact holes, local routing paths, and cut masks, where 2D design flexibility was paramount [P1, P2].

The 7nm Node and Beyond

At the 7nm FinFET node, multi-patterning complexity scaled exponentially [T2]. To define sub-40nm pitches without EUV, the industry had to chain multiple LELE steps together, leading to litho-etch-litho-etch-litho-etch (LE3) and even quadruple litho-etch (LE4) processes [P1]. The cumulative overlay error budgets and skyrocketing mask costs associated with these multi-step processes drove the development and adoption of extreme ultraviolet (EUV) lithography [T2]. Single-exposure EUV temporarily simplified patterning by replacing multi-step immersion LELE sequences with a single high-resolution pass [P1].

Related Processes

LELE integration does not operate in isolation; it is deeply intertwined with several adjacent process steps across the fabrication line:

• Dry Etching: Highly selective and anisotropic dry etching is the foundation of the LELE pattern transfer, ensuring that the first pattern acts as a robust block during the second etch pass [T1, T2, P3].
• Deposition Techniques: Film deposition methods, such as atomic layer deposition (ALD) and plasma-enhanced chemical vapor deposition (PECVD), are utilized to deposit conformable, highly uniform hard mask materials with precisely controlled physical properties [P1, A2].
• Chemical Mechanical Planarization (CMP): Prior to the second lithographic step, chemical mechanical planarization is often employed to planarize the dielectric topography, ensuring a completely flat surface to maximize the depth-of-focus window for the subsequent photoresist exposure [T2].
• BEOL Metallization: In copper dual damascene metallization schemes, LELE is highly integrated with ultra-low-k intermetal dielectrics, requiring careful etch chemistry to prevent damage to the delicate low-k dielectric materials during the repeated photoresist strip and etch steps [P1].

Future Outlook

As the industry enters the sub-2nm regime, featuring gate-all-around (GAA) nanosheets and complementary field-effect transistor (CFET) architectures, patterning complexity continues to escalate [A2]. Even with high-NA EUV lithography, single-exposure limits are again being reached, forcing the re-introduction of double patterning paradigms into the EUV regime [P4].

Next-generation EUV-LELE and hybrid self-aligned schemes are being developed to pattern ultra-dense metal lines [P1]. To overcome the overlay errors inherent to conventional LELE, research is heavily focused on area-selective ALD and atomic layer etching (ALE) [P4]. By utilizing surface-sensitive chemical reactions that deposit or remove materials only on specific target surfaces, these emerging techniques aim to provide self-aligned integration pathways, reducing the dependency on pure mechanical placement accuracy and extending the lifetime of multi-patterning technology [A1, A2].