A photoresist pattern selects where an implant is allowed across circuit regions. A gate and its spacer define local boundaries near an individual device. A self-aligned local edge does not eliminate the need to exclude other regions from the same implant.
Begin with two coordinate scales
At the circuit scale, a mask can expose one transistor type or a particular pixel region while covering others. At the device scale, the gate and spacer already present on the wafer obstruct incoming ions near their own edges. The final implanted region is determined by the combination of exposed areas and local geometry.
Calling an implant self-aligned identifies a relationship to an existing feature. It does not say that every region of the wafer receives it, or that lithographic overlay has become irrelevant to every boundary.
Process checkpoint
Understand NMOS S/D, FD Implant Mask Lithography in context
Identify the lithographic selection of NMOS and FD regions and the already formed sidewall geometry.
Process context for “Photoresist Region Selection and Spacer Offset Work at Different Scales”: 40nm BSI CMOS Image Sensor · NSDFD · Step 92
A spacer is not another circuit-selection pattern
Directional etch-back can leave dielectric along gate sidewalls after material on more horizontal surfaces is removed. That local shape introduces an offset from the gate. The regional photoresist opening can encompass the device while leaving this existing offset to control the near-gate boundary.
The same physical layer should not be described as doing both jobs without evidence. A layout opening and a sidewall seen in a cross-section answer different spatial questions.
Conditions and counterexamples
A correctly formed spacer does not prevent an implant entering an unintended unmasked circuit region. A correctly selected region does not establish a correct local spacer width or junction profile. Either error can survive while the other part of the masking system is correct.
These distinctions do not prescribe a mask size or implant angle. Ions may also scatter or redistribute later, so a mask edge is not a complete measurement of the final chemical junction.
Read both stations and explain their coexistence
Identify what the implant lithography selects, then locate the spacer left by etch-back. State which boundary follows the lithographic pattern and which follows the existing gate geometry.
The task adds a spatial masking distinction to the existing LDD–halo discussion. It does not reclassify the electrical roles of those implants, or claim that a self-aligned label proves every overlay and profile requirement has passed.
References
Silicon VLSI Technology - Full
James D. Plummer, Michael D. Deal, Peter B. Griffin
Silicon VLSI Technology · ISBN 978-0130850379