Gate Pitch, Gate Length and Channel Length: Read the Boundaries

Gate pitch, physical gate length and effective channel length describe different distances. Pitch describes repetition between neighboring gates; physical gate length describes the patterned electrode along the current direction; effective channel length belongs to an electrical device model. One value cannot be substituted for another without a definition and evidence. [T1][T2]

Start with the direction of the measurement

Imagine a row of parallel, equally wide gate lines. Along the direction perpendicular to those lines, one repeat contains a line and the space to the next line. The pitch is the repeat distance. In this simple geometry, narrowing each line while keeping its center fixed increases the intervening space without changing pitch. Moving the centers closer together changes pitch, even if line width stays unchanged. The line-and-space definition follows ordinary pattern geometry; the textbook gives it for patterned interconnects. Applying the same geometric bookkeeping to parallel gates does not turn a metal-line example into a gate-process specification. [T1]

The direction matters. A gate also extends across the transistor width. Measuring that extension is not automatically measuring the gate length along source-to-drain transport. Before comparing two drawings, identify the current direction, the gate edge and the neighboring repeated object.

Keep the layout, the physical gate and the channel separate

A designer specifies a drawn gate length. Pattern transfer produces a physical gate, and the two lengths need not be identical. The electrical channel is another quantity: its definition accounts for the source and drain boundaries relevant to the device model. Hu's discussion of channel-length extraction explicitly distinguishes drawn, physical and effective lengths. [T2]

For the node-label row, the safe rule is interpretive: obtain the actual dimension definition from the source. A label does not provide the measurement boundaries needed for any of the other rows.

A contact adds constraints, not a new definition of gate length

“Contacted gate pitch” or the historical name “contacted poly pitch” brings contact integration into the spacing discussion. A source/drain connection needs a conducting path and separation from neighboring gates. The available space therefore has to accommodate more than a bare gate edge: spacers, protection and connection geometry can matter. The textbook's spacer and contact discussion explains why these neighboring structures belong in a transistor cross-section. [T2]

That does not justify adding nominal widths from unrelated sections to calculate a universal contacted pitch. Offsets, shared regions, three-dimensional placement and the source's measurement convention must be known. Nor does “poly pitch” prove that the final working electrode is polysilicon in a replacement-gate process.

Use counterexamples to test a scaling claim

First keep the line centers fixed and reduce the physical gate length in an idealized drawing. Pitch has not changed. This is a geometric counterexample to the statement that a shorter gate always means a denser gate array.

Next keep the patterned gate unchanged but change the source/drain junction boundaries considered by an electrical model. Effective channel length can change without the same change in physical gate length. This is why a current-based extraction and an image of the electrode answer different questions. It is not a recipe for extracting channel length from an uncalibrated image. [T2]

Finally compare a contact opening with a gate line. A wider connection may improve one geometric margin while consuming room elsewhere; it does not by itself lengthen the channel. The contact-boundary comparison addresses protection and overlap, while contact versus interconnect resistance addresses a different electrical task.

Read the actual pattern-transfer station

Continue to 14nm Dummy Gate a-Si Etch, Step 91. Its final rationale section distinguishes a patterned gate from effective channel length and explains that later junction profiles and electrical definitions matter. Identify the existing gate pattern and name which later structures are still absent. This station teaches those boundaries; it does not provide a contacted-pitch measurement or an electrical extraction dataset.

As a check, write three separate labels beside your conceptual sketch: repeated gate positions, physical gate edges and electrical channel boundaries. If the sketch lacks one pair of boundaries, leave that distance unknown. A convincing drawing is not a substitute for its missing definition.

Sources

• Plummer, Deal and Griffin, Silicon VLSI Technology
• Chenming Hu, Modern Semiconductor Devices for Integrated Circuits, Chapter 6