What is the 40nm BSI CMOS Image Sensor process flow?

The 40nm BSI (Backside Illuminated) CMOS Image Sensor process flow is a specialized semiconductor manufacturing sequence for high-performance image sensors. Unlike traditional front-side illuminated (FSI) architecture, BSI places the photodiode beneath the metal interconnect layers and receives light from the wafer backside, dramatically improving quantum efficiency and low-light performance. This flow contains 417 process steps and is entirely free to access.

What is the difference between BSI and FSI image sensors?

In FSI architecture, incident light must pass through the metal interconnect layers to reach the photodiode — metal lines block and reflect some light, reducing quantum efficiency. BSI flips the wafer so light enters directly from the backside into the photodiode, bypassing the metal stack. This gives BSI sensors significantly higher sensitivity at the same pixel size, making them ideal for smartphone cameras and low-light applications.

What is the role of Deep Trench Isolation (DTI) in the 40nm CIS flow?

Deep Trench Isolation (DTI) creates physical and optical barriers between adjacent pixel photodiodes in BSI CIS. The trenches are filled with low-refractive-index material, preventing photo-generated carriers from diffusing into neighboring pixels (electrical crosstalk) and blocking oblique light from crossing pixel boundaries (optical crosstalk). This is critical for maintaining image quality as pixel pitch shrinks.

What is the role of Color Filter Array (CFA) and microlens in CIS?

The Color Filter Array sits above each pixel, arranging red, green, and blue filters in a Bayer pattern (RGGB) so each pixel captures only one color. The microlens array sits above the CFA, focusing incident light onto each pixel's active area to improve light collection efficiency. In BSI architecture, the shorter optical path and absence of metal obstruction simplify CFA and microlens alignment and increase the fill factor.

What are the key modules in the 40nm CIS process flow?

Key modules include: STI (Shallow Trench Isolation), Well formation, Gate, PD (Photodiode formation), F-DTI (Frontside Deep Trench Isolation), PMD/Contact, multi-level metal interconnect (MET0-MET6), DBI (Direct Bond Interconnect — wafer bonding), backside thinning (THIN), backside passivation (BKPAS), LS Grid (Light Shield Grid), CFA (Color Filter Array), microlens (UOCL), and Bondpad. The flow spans 42 modules and 417 process steps.

40nm BSI CMOS Image Sensor - 40nm 工艺流程

热压键合促进已对准 CIS 与 ISP 界面的接触与结合，形成支持后续退火和背面减薄的结构；结合强度和电连接需分别判断（工程实践）。

本步位于晶圆配对、两侧表面激活与对准之后，后续为 Post-Bond Anneal 和 CIS 背面研磨。前序 Flow 包含 DBI 焊盘、铜填充及金属／氧化物 CMP，因此应结合已有导体和介质界面解释键合，而不是把它视为单纯对准动作。后续退火仍是独立步骤，不能由热压完成推断全部界面演化已经结束。

接触、界面反应与导电连续性

局部空隙或污染可能使机械强度与电连接表现不同；减薄及后续热历史还会改变界面承受的载荷。

热压键合促进已对准 CIS 与 ISP 界面的接触与结合，形成支持后续退火和背面减薄的结构；结合强度和电连接需分别判断（工程实践）。

接触、界面反应与导电连续性

局部空隙或污染可能使机械强度与电连接表现不同；减薄及后续热历史还会改变界面承受的载荷。

40nm BSI CMOS Image Sensor登录后免费

工艺截面图

本步要点

原理展开

接触、界面反应与导电连续性

风险与挑战

40nm BSI CMOS Image Sensor登录后免费

工艺截面图

本步要点

原理展开

接触、界面反应与导电连续性

风险与挑战