Technical Blog
Deep dive into the physics and integration logic of semiconductor manufacturing
28nm Poly Gate Patterning Process Flow: Principles, Photolithography, and Etch Integration
Function in the Complete Flow In the 28nm Planar process flow, the gate patterning module acts as the central structural bridge between thin-film stack deposition and front-end…
28nm STI CMP Mechanism: Planarization Physics, Interfacial Chemistry, and Defect Control
Function in the Complete Flow In advanced integrated circuit manufacturing, shallow trench isolation (STI) serves as the primary structural boundary preventing parasitic leakage…
7nm Fin Recess Mechanism: Physics, Integration, and Fin Height Control
Function in the Complete Flow In sub-10nm logic manufacturing, the fin recess etch serves as the critical dimensional-setting step that transforms a planarized shallow trench…
7nm Metal Gate CMP Mechanism: Physical Chemistry, Planarization Stop Control, and Integration Dynamics
Function in the Complete Flow In advanced replacement metal gate (RMG) FinFET integration, sacrificial poly-silicon dummy gates are removed and replaced with high-k gate…
7nm Dummy Gate Etch Over Fins: Physical Mechanisms, Integration Logic, and Downstream Reliability
Function in the Complete Flow In 7nm Fin-shaped Field-Effect Transistor (FinFET) logic manufacturing using a replacement metal gate (RMG) scheme, dummy gate patterning is a…
14nm FinFET Dummy-Gate Silicon Etch Over Fins: Physical Mechanisms, Profile Control, and Module Integration
Function in the Complete Flow In advanced multi-gate architecture integration, particularly within the 14nm gate template definition, the formation of functional transistor gate…
Gate-Contact Tungsten Fill and CMP Integration Principles in 14nm FinFET Technology
Function in the Complete Flow In advanced middle-of-the-line (MOL) processing for 14nm FinFET architectures, gate contact metallization serves as the critical conductive bridge…
Mastering the Upper OCL Reflow Mechanism in 40nm BSI CMOS Image Sensors: Physics, Surface Free Energy, and Optical Integration
Function in the Complete Flow In a modern 40nm backside illuminated (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor (CIS), the optical stack above the silicon…
Contact Barrier (CB) Dielectric Etch in 28nm: Physics, Integration Mechanisms, and Device Reliability
Function in the Complete Flow In a 28nm Planar process flow, the contact barrier (CB) dielectric etch is the pivotal pattern-transfer step that opens vertical access vias through…
P-Pinning Implant and Surface-Potential Control in 40nm BSI CIS Integration
Function in the Complete Flow In modern image sensor manufacturing, the formation of the surface pinning layer represents a cornerstone step within the frontside photodiode module.
Selective eSi Source-Drain Integration at 7nm: Physics, Chemistry, and Module Integration
Function in the Complete Flow In sub-10nm logic manufacturing, the integration of selective epitaxial silicon (eSi) in the source and drain regions of n-channel Field-Effect…
Selective Si and SiGe Epitaxy Integration at 14nm: Principles, Strain Kinetics, and Integration Logic
Function in the Complete Flow In modern 14nm FinFET logic fabrication, raised source/drain epitaxy plays a foundational role by simultaneously managing parasitic series…