Where does LPCVD fit in a semiconductor flow?
LPCVD is a deposition approach, not a single fixed station shared by every semiconductor flow. Its place depends on what the deposited film must do and what already exists on the wafer. A film used to support pattern transfer faces different requirements from a gate-related layer or an insulating film. The same material name does not establish the deposition method.
This article explains how to read those integration relationships. Start with three questions: what structure needs the film, which later step uses or removes it, and which earlier structure limits its thermal or chemical exposure? These questions connect the deposition mechanism to the rest of the process without turning the explanation into operating instructions.
Process map
28nm Planar Flow
Trace isolation, gate and source/drain module relationships in the 28nm overview without assuming a deposition recipe.
Begin with the film's job
A hard mask preserves a pattern while another material is etched. Its usefulness depends on the relative resistance of the materials involved, continuity and the ability to remove it without unacceptable damage. Calling a film dense or uniform is not enough to establish that it is a suitable mask.
A spacer-related film is deposited before a directional removal step leaves material beside an existing feature. Coverage helps establish the initial geometry; etch behavior helps determine what remains. Deposition and removal therefore contribute different parts of the final structure. Neither one can be understood from the other alone.
A gate-related film must also be considered electrically. If a deposited layer is temporary, it must survive intermediate processing and later be removed appropriately. If it remains in the final device, its interfaces and electrical function become part of the device itself. The distinction between temporary and final layers is more useful than assuming every film in a gate module serves the same purpose.
Earlier structures constrain later deposition
Thermal processing can change dopant distributions, interfaces and film stress. A deposition option that suits an early stage may be unsuitable after more sensitive structures exist. This is why an integration sequence matters even when the desired final film appears similar.
The constraint is cumulative: different exposures contribute to the wafer's history. Replacing one deposition step cannot be assessed only through its growth rate. Film quality, surface preparation, later removal and the response of previously formed structures remain relevant. No universal temperature or pressure choice follows from a node name.
Later steps reveal whether the film was suitable
A deposited film can look continuous yet behave poorly during a subsequent etch, cleaning operation or thermal exposure. Residual impurities, porosity and stress can change how it responds. Conversely, a material that is useful as a temporary process aid need not have the same properties required of a permanent device layer.
Coverage also needs to be interpreted against the next operation. Coating a sidewall and filling an opening are different tasks. A coating that narrows the opening may complicate later filling even when its local coverage is good. These relationships explain why deposition cannot be optimized independently of the surrounding steps.
Read the related Flow as a map
The 28nm Planar Flow overview relates isolation, gate formation, source/drain processing, replacement metal gate and interconnect modules. Use it to distinguish the structures that exist before a module from the structures that module prepares for later processing.
The overview does not certify that every listed deposition uses LPCVD. It also describes one teaching flow, not every process sold under the same node label. Its useful next task is to identify a film's structural role and its neighbors. The LPCVD mechanism article explains why transport, surface reaction and geometry must then be considered separately.
References
Silicon VLSI Technology - Full
James D. Plummer, Michael D. Deal, Peter B. Griffin
Silicon VLSI Technology · ISBN 978-0130850379