Single and dual damascene differ in how dielectric patterning is grouped with metal filling. In a single-damascene sequence, a patterned level is filled and planarized separately. In dual damascene, a connected via and line cavity are prepared before a shared metal fill and planarization sequence. “Dual” does not mean depositing two metals.
Start with the two jobs an interconnect must do
A line carries current mainly along a wiring level. A via connects wiring at different heights. In a damascene structure, dielectric openings establish where these conductors will remain. Metal initially also covers the field surface; planarization removes that overburden to separate neighboring conductors.
This distinction between an opening and its eventual conductor matters. A cross-section containing a trench and a hole is not necessarily a finished electrical connection. Their surfaces still need the appropriate interfaces and continuous metal fill.
Process checkpoint
Understand V1M2 Etch in context
Inspect the M2 via-and-trench opening before barrier, seed and copper fill.
Process context for “Single vs Dual Damascene: Follow the Fill Sequence”: 28nm Planar Flow · M2 · Step 218
Compare the integration sequence
| Question | Separate single-damascene levels | Dual damascene |
|---|---|---|
| When is the via filled? | In its own patterned level | After the connected via and trench cavity is prepared |
| When is the line filled? | In another fill sequence | Together with the via cavity |
| What is coupled? | The handoff between separately completed levels | Via/trench patterning, interface preparation and common fill |
| What must planarization leave? | The conductor in the current opening | The line and its connection through the via |
This is a conceptual comparison of via-plus-line construction, not a rule that every single-damascene operation creates a via. A single-damascene level can also define a line.
Shared filling changes where the difficult handoff occurs
Completing the via separately provides an intermediate surface before line formation. That does not make the process automatically easier: the next level still has to land on the completed conductor, and its interface must remain suitable for electrical connection.
Dual damascene removes that separate via-completion handoff from the compared sequence, but the combined cavity introduces another problem. The transition between trench and via has to survive patterning and cleaning while remaining accessible for interface formation and metal growth. A well-defined trench cannot compensate for a blocked via bottom.
Via-first and trench-first are alternative ways of preparing this combined cavity. They are subdivisions of dual damascene, not alternatives to the single-versus-dual distinction. The literature describes several such integration sequences; their suitability depends on the actual stack and patterning constraints.
A useful cross-section reading exercise
Imagine two process snapshots with the same final wiring shape. In the first sequence, a filled via already exists when the line opening is formed. In the second, the via remains an empty opening until the line trench is also ready. The finished drawing alone hides the difference; the intermediate fill state reveals it.
Now ask where an unwanted interface or residue could interrupt current. In the first sequence, examine the connection to the already completed via. In the second, examine access through the combined cavity and the exposed landing surface. This exercise distinguishes integration risks without asserting that either route always has better resistance or yield.
Source links
References
Silicon VLSI Technology - Full
James D. Plummer, Michael D. Deal, Peter B. Griffin
Silicon VLSI Technology · ISBN 978-0130850379
Overview of dual damascene integration schemes in Cu BEOL integration
J. Kriz, C. Angelkort, M. Czekalla, S. Huth, D. Meinhold, A. Pohl et al.