P+ Contact Implant: Physics, Process Principles, and Technology Node Evolution

Introduction

In modern semiconductor manufacturing, establishing highly reliable, low-resistance electrical connections to the p-type silicon substrate or well is a foundational requirement for stable integrated circuit (IC) performance. The P+ contact implant is a critical step in the front-end-of-line (FEOL) process flow designed to create a heavily doped p-type region ($p^+$) directly beneath metal or silicide contact plugs. This localized, high-concentration doping region is essential for transforming rectifying metal-semiconductor interfaces into low-resistance ohmic contacts.

Without a dedicated P+ contact implant, contacts to moderately or lightly doped p-type regions exhibit high Schottky barrier heights and wide depletion widths, severely impeding majority carrier (hole) transport and introducing parasitic resistance. The challenge of fabricating good ohmic contacts has been increasing with device miniaturization [T2]. The P+ contact implant is deployed across several key functional areas in silicon CMOS design. Most notably, it is used to construct the $V_{SS}$ ground contact, which ties the p-type well (p-well) or substrate to the lowest system potential to suppress parasitic latch-up and drain transient charges. Furthermore, in image sensor pixels, such as CMOS image sensors (CIS), p-well ground contacts manage the reference potential, draining unwanted thermal carriers and suppressing pixel noise.

Device Physics & Mechanism

At the interface between a contact metal (or metal silicide) and a semiconductor, a potential barrier known as the Schottky barrier forms due to work function differences and surface state pinning. For p-type silicon, the energy barrier height ($Phi_{Bp}$) determines hole transport across the junction. In lightly or moderately doped semiconductors, current flow is dominated by thermionic emission, where carriers must acquire sufficient thermal energy to cross over the barrier, yielding non-linear, rectifying contact behavior.

To establish an ohmic contact with negligible resistance, the dominant transport mechanism must transition from thermionic emission to field emission (quantum-mechanical tunneling). The traditional method to reduce the contact resistance for silicon is to decrease the depletion region width by locally doping near the silicon-metal junction [P4]. The depletion region width ($W$) of a metal-semiconductor junction is inversely proportional to the square root of the active dopant concentration ($N_A$):

$$W \approx \sqrt{\frac{2\varepsilon_s \phi_{bi}}{q N_A}}$$

where $\varepsilon_s$ is the semiconductor permittivity, $q$ is the elementary charge, and $\phi_{bi}$ is the built-in potential.

By executing a heavy P+ contact implant, the active acceptor concentration ($N_A$) at the silicon surface is elevated toward or beyond high acceptor concentration. This heavy doping dramatically narrows the depletion width ($W$) to a few nanometers, enabling holes to tunnel directly through the barrier. Consequently, specific contact resistivity ($\rho_c$) drops dramatically, yielding a linear ohmic contact.

Beyond minimizing contact resistance, the P+ contact implant plays a structural role in suppressing p-well de-biasing and parasitic latch-up. In CMOS architectures, transient events—such as ionizing radiation or high-voltage overshoot—can inject excess electron-hole pairs into the p-well. If hole extraction is delayed due to high well resistance or poor contact resistance, the local p-well potential rises relative to the ground terminal. This de-biasing can forward-bias adjacent $n^+/p\text{-well}$ junctions, triggering the parasitic SCR (silicon-controlled rectifier) structure inherent to CMOS technology. A well-designed P+ contact implant ensures a low-resistance path to quickly extract excess holes and maintain electrostatic potential stability.

Process Principles

The physical implementation of the P+ contact implant relies on ion implantation, accelerating energetic acceptor ions into the target silicon regions.

Dopant Species Selection

Boron ($B$) is the standard acceptor species for p-type silicon. However, because elemental boron has a low atomic mass, it suffers from severe axial and lateral straggle during implantation, as well as significant crystal channeling effects. Furthermore, boron exhibits high diffusivity during thermal activation. To achieve shallower and more abrupt junction profiles, boron difluoride ($BF_2^+$) is frequently chosen as the implant species. Upon impacting the silicon substrate, the heavier $BF_2^+$ molecular ion dissociates, amorphizing the surface silicon layer and self-suppressing channeling, which results in a tighter, shallower projected range ($R_p$).

Implantation Energy and Dose

Implantation energy dictates the projected depth ($R_p$) of the dopant peak. For contact implants, low-to-moderate acceleration energy is preferred to concentrate dopants near the silicide-silicon interface without punching through underlying shallow junction boundaries. The implantation dose is set to high levels to ensure that, after electrical activation, the active carrier concentration approaches the solid solubility limit of boron in silicon.

Activation Annealing and Damage Recovery

High-dose ion implantation damages the silicon single-crystal lattice, generating point defects and amorphous layers. Subsequent thermal processing using rapid thermal annealing (RTA) is required to recrystallize the lattice and substitute boron atoms onto active substitutional lattice sites. The thermal budget must be carefully balanced: sufficient thermal energy is required to dissolve extended lattice defects, yet excessive thermal budget causes unwanted dopant diffusion, degrading shallow junction abrupness.

Engineering Challenges & Failure Modes

Integrating high-dose P+ contact implants into advanced CMOS integration flows presents several critical physical failure modes:

• Junction Leakage from End-of-Range (EOR) Defects: High-dose implants create an amorphized layer. During thermal recrystallization, end-of-range dislocation loops form near the original amorphous-crystalline interface. If these defects reside within the depletion region of an adjacent active PN junction, they act as mid-gap generation-recombination centers, driving up reverse junction leakage currents.
• P-well De-Biasing and Latch-up Susceptibility: If the contact implant dose is insufficiently activated or masked by topographical defects, the high contact resistance leads to localized potential collapse during transient electrical surges, triggering parasitic latch-up.
• Edge Breakdown and Noise in CIS/SPAD Devices: In high-voltage or sensitive optoelectronic devices (such as single-photon avalanche diodes or image sensor pixels), placing a abrupt, highly doped P+ contact near a shallow trench isolation (STI) corner accentuates electric field crowding. Combined with STI interface state traps, this elevated field induces premature edge breakdown, increasing dark count rates (DCR) and pixel noise.

Technology Node Evolution

Planar Nodes (28nm and Above)

In conventional planar CMOS architectures, the P+ contact implant is self-aligned to the gate electrode and sidewall spacers. The implant enters the planar source/drain diffusion regions and substrate contact pick-offs. Thermal activation relies on spike RTA, and silicidation (such as $NiSi$) follows to form the low-resistance contact interface.

3D Architecture Era (14nm/7nm FinFET)

With the transition to fin field effect transistor (FinFET) nodes, executing uniform implants into tall, narrow 3D silicon fins became extremely challenging. Conventional line-of-sight ion implantation causes severe shadowing effects and non-uniform doping across the fin sidewalls. To maintain conformal contact doping, process flows adopted conformal plasma doping (PLAD) alongside in-situ boron-doped silicon-germanium ($SiGe:B$) epitaxy in the source/drain contacts, using strain engineering and high dopant incorporation simultaneously.

Advanced Sub-5nm and Beyond

At advanced nodes, scaling of contact area causes interface contact resistance to dominate transistor total parasitic resistance. Standard ion implantation followed by conventional RTA is constrained by equilibrium solid solubility limits. To push active dopant concentration higher without broadening the dopant profile, pre-contact trench implants combined with short-pulse laser thermal annealing are integrated into the contact module. Laser-assisted processing can be utilized to form ultra-shallow junctions with very high, metastable active doping concentrations [T1].

Integration and Adjacent Modules

The P+ contact implant relies on tight coordination with upstream and downstream process steps:

• Lithography: Defines the contact opening windows, where misalignment can cause unwanted bridging to nearby N+ regions or inadequate well tie coverage.
• Contact Etch: Before silicidation, dry etching opens contact vias through the dielectric layers. Polymer residues or lattice damage from etching must be cleaned to expose pristine silicon for contact doping.
• Silicidation & Metallization: Silicides (e.g., $TiSi_2$, $CoSi_2$, or $NiSi$) lower the Schottky barrier height, while the underlying P+ implant narrows the barrier width, together minimizing total contact resistance.
• Planarization: Chemical mechanical planarization (CMP) maintains surface planarity to ensure uniform focus during contact photolithography and precise implant depth control across the wafer.