40nm BSI CMOS Image Sensor Metal-Three Interconnect Integration: Process Flow Principles and Device Physics

Role in the Complete Flow

In the 40nm backside illumination (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor fabrication sequence, the metal-three (MET3) interconnect integration module occupies a critical position within the multilevel metallization stack [A2]. By the time the flow reaches this module, the wafer has already passed through the photodiode formation, pixel transistor fabrication, and lower-level metal interconnect layers that wire the pixel array and peripheral circuitry [A2]. The MET3 module receives a wafer surface where the second interlayer dielectric (ILD) and via-two structures have been completed, providing the electrical bridge from metal-two lines up toward the higher interconnect levels [T1]. (Engineering Practice)

The primary deliverable of the MET3 module is a patterned metal layer that serves as an intermediate signal routing plane, connecting column-parallel readout signals, timing control lines, and analog signal paths between the pixel array and peripheral logic circuits. In BSI CMOS image sensors, the frontside metallization also functions as a reflector layer that can redirect photons back toward the photodiode, boosting quantum efficiency (QE) [P2]. This dual role—electrical routing and optical enhancement—makes the MET3 layer uniquely important compared to a generic logic process metal level [A2]. The 40nm BSI CMOS Image Sensor process flow depends on each metal level fulfilling both electrical and optical requirements simultaneously [P3].

The MET3 module must deliver a planarized, low-resistance interconnect with well-defined trench profiles, intact barrier and seed layers, and minimal parasitic capacitance to adjacent structures [A2]. Any discontinuity or excessive roughness at this level propagates upward, degrading subsequent dielectric planarization and metal-four patterning fidelity [P1].

Entry State and Sequence Logic

Upstream Dependencies

The MET3 module process flow begins after the completion of the third interlayer dielectric (ILD3) deposition and planarization [T1]. The 40nm BSI CMOS Image Sensor third interlayer dielectric integration process flow establishes the dielectric isolation between metal-two and metal-three, and its surface topography directly constrains MET3 lithography and etch performance [P1]. A poorly planarized ILD3 surface creates depth-of-focus challenges during METAL 3 TRENCH - Photo exposure, causing trench-width variation that cascades into metal line resistance non-uniformity [P1]. Prior to ILD3, the 40nm BSI CMOS Image Sensor via-two integration process flow formed the vertical interconnect structures that electrically link metal-two to the MET3 layer [A2]. The integrity of these via-two connections determines whether MET3 can reliably route signals without open-circuit failures or excessive contact resistance (Engineering Practice). (Engineering Practice)

Downstream Deliverables

Once MET3 patterning and metal fill are complete, the module hands off a planarized metal surface to the subsequent ILD4 deposition and via-three formation steps. The MET3 surface planarity, metal line roughness, and barrier layer integrity all influence the quality of the next dielectric deposition and the alignment budget for via-three lithography [P1]. In BSI image sensors, MET3 also contributes to the optical stack: its reflectivity and surface texture affect how photons are redirected within the pixel, particularly for near-infrared wavelengths where the silicon absorption depth is large and multiple photon passes through the epitaxial layer are beneficial [P1]. Thus, the MET3 module is not merely an electrical interconnect—it is part of the optical path engineering that defines sensor sensitivity [A2].

Physical and Chemical Mechanisms

METAL 3 TRENCH - Photo Integration Principles

The METAL 3 TRENCH - Photo step is the photolithographic patterning operation that defines the trenches into which metal will subsequently be deposited (Engineering Practice). At the 40nm technology node, krypton fluoride (KrF) lithography is commonly employed for metal-layer patterning in image sensor processes, where the critical dimension requirements are moderated by the larger pixel pitch compared to advanced logic nodes [P1]. The fundamental principle involves exposing a photoresist layer through a reticle pattern, where the incident photons induce chemical changes in the resist's photoactive compound [P1]. In positive-tone resists, exposure degrades the polymer backbone in the irradiated regions, rendering them soluble in the developer solution [P1]. The resulting resist pattern serves as an etch mask for transferring the trench geometry into the underlying dielectric [A2]. The interaction between the photoresist and the underlying ILD3 topography is governed by the principles of depth-of-focus and process window [P1]. A non-planar substrate causes local focus variations, and at scaled dimensions, even small topographic excursions can cause resist sidewall angle changes that propagate into trench profile variation [T1]. This is why chemical mechanical planarization (CMP) of ILD3 before MET3 lithography is essential—the flatter the surface, the wider the usable focus window (Engineering Practice).

Trench Etch Chemistry

After resist patterning, a dry etch step transfers the trench pattern into the dielectric (Engineering Practice). The etch process typically employs fluorocarbon-based plasmas that combine physical ion bombardment with chemical etching of the dielectric material [P1]. The etch chemistry must achieve high selectivity to the resist mask (to preserve critical dimension control) and to the underlying via-two metal (to avoid erosion of electrical contacts) [P1]. (Engineering Practice)

The etch byproducts are volatile silicon-fluorine compounds that are pumped away, while polymer passivation on the trench sidewalls controls the sidewall angle and prevents lateral etching. The balance between polymer deposition and etch rate determines the final trench profile—too much polymer leads to tapered walls that constrain metal fill, while too little causes undercutting that compromises structural integrity (Engineering Practice). (Engineering Practice)

Barrier and Seed Deposition

Following trench formation, a diffusion barrier layer (typically a refractory metal nitride) is deposited conformally along the trench sidewalls and floor. The barrier prevents metal atoms from diffusing into the surrounding dielectric or underlying silicon, which would introduce dark current and reliability degradation in the image sensor [A1]. A seed layer is then deposited to provide a conductive nucleation surface for subsequent bulk metal fill [P1]. (Engineering Practice)

The barrier deposition mechanism relies on atomic layer deposition (ALD) or physical vapor deposition (PVD), where precursor molecules or sputtered atoms adsorb onto the trench surfaces and react to form a thin, conformal film. The conformality is critical: at the bottom of narrow trenches, shadowing effects can thin the barrier, creating weak points for metal diffusion (Engineering Practice). In BSI image sensors, such diffusion is particularly harmful because metal contamination in the photodiode region increases dark current and degrades low-light performance [P1].

Metal Fill and Planarization

The bulk metal fill is achieved through electrochemical deposition, where metal ions from a plating solution are reduced at the seed-layer surface (Engineering Practice). The plating front grows from the seed layer outward, filling the trench from the bottom up (Engineering Practice). The fill mechanism depends on the competition between conformal growth and superfilling additives that accelerate deposition in recessed features (Engineering Practice). (Engineering Practice)

After fill, CMP removes the overburden metal and barrier layer from the field regions, leaving metal only within the trenches. The CMP mechanism combines mechanical abrasion by silica slurry particles with chemical dissolution of the metal surface (Engineering Practice). The selectivity between metal and dielectric during CMP determines the degree of metal dishing—excessive dishing reduces the effective metal cross-section and increases line resistance, while insufficient planarization leaves metal residue that causes short circuits between adjacent lines [T1].

Interfaces and Failure Propagation

ILD3-to-MET3 Interface

The interface between the ILD3 dielectric and the MET3 metal lines is a primary site for failure propagation [T1]. If the ILD3 surface is not sufficiently planarized, the MET3 trench etch encounters varying dielectric thicknesses across the wafer, producing non-uniform trench depths [P1]. Shallower trenches reduce metal cross-sectional area, increasing resistance and degrading signal integrity in column readout paths (Engineering Practice). Deeper trenches risk penetrating into via-two structures, creating short circuits or barrier layer compromise (Engineering Practice). (Engineering Practice)

The tradeoff direction is clear: improving ILD3 planarity widens the MET3 process window but requires more aggressive CMP, which can thin the dielectric and increase parasitic capacitance between metal-two and metal-three. Higher parasitic capacitance degrades signal bandwidth and increases crosstalk between adjacent interconnect lines, which is particularly problematic for the sensitive analog signals routed through MET3 in image sensor readout paths [P4].

MET3-to-ILD4 Interface

Downstream, the MET3 surface condition directly affects ILD4 deposition quality [T1]. Metal dishing or barrier layer residue on the field regions creates topographic steps that challenge via-three lithography alignment and focus [A2]. If the MET3 surface has excessive copper hillocks or nodules—growth defects that can form during thermal cycles—the subsequent dielectric deposition may exhibit voids or weak adhesion at these sites [T1]. The barrier layer integrity at the MET3-to-ILD4 interface is also critical for preventing metal migration into upper dielectric layers [T1]. In stacked image sensor architectures, where an interposer layer connects the pixel array chip to a logic chip, barrier layers must suppress both vertical and lateral metal diffusion [A1][A2]. A compromised barrier allows metal atoms to migrate into the interposer dielectric, creating parasitic charge traps that increase dark current and fixed-pattern noise in the image sensor [P1].

Optical Interaction in BSI Architecture

In BSI CMOS image sensors, the frontside metal layers—including MET3—serve as optical reflectors that redirect unabsorbed photons back through the epitaxial layer for a second absorption pass [P3]. The reflectivity of MET3 depends on the metal surface roughness and the dielectric stack above it [P1]. A rough MET3 surface scatters photons diffusely, reducing the directed reflection that enhances QE, particularly for near-infrared light where the silicon absorption coefficient is low and multiple passes are needed [P1][P2].

The tradeoff here is between electrical performance (which favors smooth, low-resistance metal lines) and optical performance (which also favors smooth surfaces but with specific dielectric stack thicknesses tuned for constructive interference) [P1]. The MET3 module must therefore satisfy both electrical and optical constraints simultaneously, a requirement absent in generic logic process metal layers [A2].

Walk the Real Module

To understand the 40nm metal-three interconnect integration in practice, engineers can explore the step-by-step interactive process flow [T1]. The module begins with the METAL 3 TRENCH - Photo step, where KrF lithography patterns the trench resist on the planarized ILD3 surface, followed by dielectric etch, barrier and seed deposition, metal fill, and CMP planarization (Engineering Practice). Each step's entry conditions, process mechanisms, and exit deliverables are documented in the interactive flow (Engineering Practice).

Open MET3 Step 184 in the interactive flow

This interactive resource allows engineers to trace the causal chain from the incoming wafer state through each unit process step, observing how the MET3 module process flow interfaces with upstream ILD3 and via-two structures and how it delivers the planarized metal surface required by downstream ILD4 and via-three integration [T1]. The step-level granularity helps identify where process window margins are tightest and where failure modes are most likely to originate (Engineering Practice).

Related Learning Paths

Engineers studying the MET3 module should also explore adjacent process modules that share integration interfaces:

• The 40nm BSI CMOS Image Sensor process flow provides the complete module-level overview, showing how MET3 fits within the full fabrication sequence from photodiode formation through final passivation [P3].
• The 40nm BSI CMOS Image Sensor third interlayer dielectric integration process flow details the upstream dielectric module whose planarity directly governs MET3 lithography quality [P1].
• The 40nm BSI CMOS Image Sensor via-two integration process flow explains the vertical interconnect structures that MET3 must electrically connect to, and whose integrity constrains MET3 trench etch depth limits [A2].

These adjacent modules form the integration chain that determines whether the MET3 layer can achieve its dual electrical and optical performance targets [P1].

Future Outlook

The evolution of BSI CMOS image sensors is driving several trends that will reshape metal interconnect integration at the MET3 level and beyond [P3]. Three-dimensional stacked image sensors, where a pixel array chip is bonded to a separate logic chip through an interposer layer, are becoming increasingly prevalent [P3][A1]. In these architectures, the MET3 layer may serve as part of the bonding interface or as a shielding structure that suppresses electromagnetic coupling between the pixel array and logic circuits [A2]. The interposer concept introduces grounded metal shielding regions spatially separated from signal-carrying interconnects, requiring new layout and process integration approaches [A2].

As pixel sizes continue to shrink and pixel arrays grow in resolution, the metal interconnect density at MET3 increases, tightening the process window for trench lithography and metal fill [A2]. The migration from KrF to argon fluoride (ArF) lithography for selected critical metal layers may become necessary, though the cost and complexity tradeoffs differ from logic processes due to the larger pixel pitch in image sensors [A1]. (Engineering Practice)

Another emerging direction is the integration of metal grid structures and deep trench isolation within the pixel region to reduce optical and electrical crosstalk [P2]. These structures interact with the frontside metal stack, including MET3, and require coordinated process design to ensure that metal reflectivity, parasitic capacitance, and dark current performance are simultaneously optimized [P1]. Research into novel barrier materials with improved conformality and diffusion resistance is also ongoing, driven by the need to suppress metal contamination in increasingly sensitive photodiode structures [P1].

Finally, the push toward higher dynamic range and wider spectral response in image sensors places additional demands on the metal interconnect stack [A2]. The LOFIC (lateral overflow integration capacitor) structures described in recent work require carefully engineered metal routing that does not introduce parasitic capacitance degrading the floating diffusion node [P1]. As these architectural innovations propagate into production, the MET3 module will need to accommodate new routing topologies and tighter electrical isolation requirements, reinforcing its central role in image sensor performance [A2].