40nm BSI CMOS Image Sensor Metal-Three Interconnect Integration: Process Flow Principles and Device Physics

Role in the Complete Flow

In the 40nm backside illumination (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor fabrication sequence, the metal-three (MET3) interconnect integration module occupies a critical position within the multilevel metallization stack. By the time the flow reaches this module, the wafer has already passed through photodiode formation, pixel transistor fabrication, and lower-level metal interconnect layers that wire the pixel array and peripheral circuitry. The MET3 module receives a wafer surface where the second interlayer dielectric (ILD2) and via-two structures have been completed, providing the electrical bridge from metal-two lines up toward higher interconnect levels.

In backside illumination architectures, photons enter through the back of the substrate to avoid light absorption by frontside gate structures and metallization layers [T2]. The primary deliverable of the MET3 module is a patterned metal layer that serves as an intermediate signal routing plane, connecting column-parallel readout signals, timing control lines, and analog signal paths between the pixel array and peripheral logic circuits. In BSI CMOS image sensors, the frontside metallization also functions as a reflector layer that can redirect unabsorbed photons back toward the photodiode, boosting quantum efficiency. This dual role—electrical routing and optical enhancement—makes the MET3 layer uniquely important compared to a generic logic process metal level. The 40nm BSI CMOS Image Sensor process flow depends on each metal level fulfilling both electrical and optical requirements simultaneously.

The MET3 module must deliver a planarized, low-resistance interconnect with well-defined trench profiles, intact barrier and seed layers, and minimal parasitic capacitance to adjacent structures. Any discontinuity or excessive roughness at this level propagates upward, degrading subsequent dielectric planarization and metal-four patterning fidelity.

Entry State and Sequence Logic

Upstream Dependencies

The MET3 module process flow begins after the completion of the via-two (V2) etch and clean operations within the second interlayer dielectric (ILD2) stack. The 40nm BSI CMOS Image Sensor via-two integration process flow formed the vertical interconnect structures that electrically link metal-two to the MET3 layer. The integrity of these via-two connections determines whether MET3 can reliably route signals without open-circuit failures or excessive contact resistance. Prior to V2, the 40nm BSI CMOS Image Sensor metal-two interconnect integration process flow established the horizontal wiring layer beneath ILD2. A poorly planarized ILD2 surface creates depth-of-focus challenges during trench photo exposure, causing trench-width variation that cascades into metal line resistance non-uniformity.

Downstream Deliverables

Once MET3 patterning and metal fill are complete, the module hands off a planarized metal surface to the subsequent third interlayer dielectric (ILD3) deposition and via-three formation steps. The 40nm BSI CMOS Image Sensor third interlayer dielectric integration process flow establishes dielectric isolation between metal-three and metal-four. The MET3 surface planarity, metal line roughness, and barrier layer integrity all influence the quality of the ILD3 deposition and the alignment budget for via-three lithography. In BSI image sensors, MET3 also contributes to the optical stack: its reflectivity and surface texture affect how photons are redirected within the pixel, particularly for near-infrared wavelengths where the silicon absorption depth is large and multiple photon passes through the epitaxial layer are beneficial. Thus, the MET3 module is part of the optical path engineering that defines sensor sensitivity.

Physical and Chemical Mechanisms

Trench Lithography and Patterning

The trench photolithography step defines the geometric openings into which barrier and conductive metals will subsequently be deposited. At the 40nm technology node, krypton fluoride (KrF) optical lithography is commonly employed for metal-layer patterning in image sensor processes, where critical dimension requirements are moderated by pixel pitch constraints. The fundamental mechanism relies on exposing a photoresist layer through a photomask, where incident photons induce chemical cleavage in the resist polymer matrix. In positive-tone resist systems, exposure renders the irradiated polymer chains soluble in alkaline developer solutions.

Because the incoming wafer contains open V2 cavities etched into ILD2, an organic bottom anti-reflective coating (BARC) or sacrificial planarizing material is first spin-coated to fill the vias and establish a flat topographic baseline. During the post-development rinse, the mechanical strength of the resist must be sufficient to withstand capillary forces to prevent pattern collapse before serving as an etch mask for transferring the trench geometry into the underlying dielectric. The interaction between the photoresist and underlying ILD2 topography is governed by depth-of-focus principles, where resolution is modeled by Rayleigh's equation R = k1 * lambda / NA. Non-planar dielectric substrates induce localized focus shifts, leading to resist line-width variations and altered sidewall angles. Prior chemical mechanical planarization (CMP) of the ILD2 layer is therefore essential to widen the available depth-of-focus window.

Trench Etch Chemistry

Following resist patterning, reactive ion etching (RIE) transfers the trench geometry into the upper ILD2 dielectric layer. The plasma chemistry typically utilizes fluorocarbon gases combined with argon and oxygen diluents. Fluorocarbon radicals chemically react with the silicon oxide matrix to form volatile SiF4 and CO2 byproducts, while accelerated positive ions provide directional physical bombardment.

To achieve vertical sidewalls without undercutting, the etch chemistry balances isotropic chemical removal with polymer passivation. Polymerizing fluorocarbon species deposit a thin protective film on the trench sidewalls, shielding them from lateral radical attack. Meanwhile, vertical ion flux continuously clears the polymer from the trench floor, enabling anisotropic downward etching. High selectivity to the underlying via-two metal landing pads is mandatory to prevent via recess or contact erosion.

Barrier and Seed Deposition

After trench formation and photoresist strip/clean, a thin diffusion barrier layer—typically composed of tantalum and tantalum nitride (Ta/TaN)—is deposited conformally across the trench floor and sidewalls. Tantalum-based liners prevent copper atoms from migrating into the adjacent inter-metal dielectric and underlying silicon substrate. Copper diffusion into photodiode regions creates mid-gap trap centers that elevate dark current and cause single-pixel white spot defects.

Physical vapor deposition (PVD) or atomic layer deposition (ALD) techniques are utilized to deposit the liner stack. Achieving high conformality at the trench bottom and lower sidewalls is critical; insufficient sidewall coverage allows copper drift under thermal stress. Following barrier deposition, a continuous copper seed layer is sputtered to provide a conductive nucleation bed for the subsequent electroplating operation.

Metal Fill and Planarization

Bulk conductor fill is accomplished through electrochemical deposition (ECD) of copper. The plating bath contains dissolved copper sulfate along with organic additives—suppressors, accelerators, and levelers—that modulate localized deposition rates. Accelerators accumulate preferentially at the trench bottom, enhancing local plating velocity, while suppressors adsorb onto upper corners to inhibit premature pinch-off. This bottom-up fill mechanism (superfilling) ensures void-free copper fill even in narrow interconnect trenches.

Following electroplating, chemical mechanical planarization removes the excess overburden copper and tantalum liner from the field regions, isolating discrete conductor lines within the trenches. CMP utilizes a chemical slurry containing oxidizing agents, complexing chemicals, and abrasive particles. Signal propagation speed along the metal line is governed by the RC time delay, which scales with both line resistance and inter-metal dielectric capacitance [T1]. Controlling metal dishing (unwanted copper erosion in wide lines) and dielectric erosion is vital to maintain consistent line resistance and uniform RC delay characteristics.

Interfaces and Failure Propagation

ILD2-to-MET3 Interface

The interface between the ILD2 dielectric and the MET3 metal lines represents a critical junction for process window control. Incomplete planarization of ILD2 causes varying dielectric thickness across the wafer, resulting in non-uniform MET3 trench depths after RIE. Shallower trenches restrict the copper cross-sectional area, elevating interconnect line resistance and degrading signal bandwidth in column readout paths. Conversely, over-etching into via-two structures risks exposing via sidewalls, compromising barrier integrity and provoking inter-layer short circuits.

A fundamental integration tradeoff exists between ILD2 planarity and dielectric thickness margin. Extended ILD2 CMP improves lithographic focus budgets but reduces the total dielectric thickness separating metal-two from metal-three, thereby increasing parasitic inter-metal capacitance.

MET3-to-ILD3 Interface

The post-CMP surface state of the MET3 layer directly dictates the deposition quality of the subsequent ILD3 dielectric layer. Copper dishing or residual tantalum film fragments left on field oxide regions produce topographic steps that scatter light during via-three lithography, compromising alignment accuracy. Thermal cycling during downstream processing can trigger copper stress-induced voiding or hillock growth if the upper capping layer does not provide adequate mechanical confinement.

Furthermore, failure of the capping diffusion barrier at the MET3-to-ILD3 interface allows copper ion migration into upper dielectric layers under electrical bias. In stacked sensor configurations, degraded inter-metal barriers induce parasitic charge trapping, which manifests as elevated fixed-pattern noise and image lag.

Optical Interaction in BSI Architecture

In BSI CMOS image sensors, the frontside metallization stack—including the MET3 layer—acts as an optical mirror array positioned beneath the silicon epitaxial layer. Photons with longer wavelengths (such as red and near-infrared light) pass through the silicon substrate without being fully absorbed on their initial transit. The metallic surface of MET3 reflects these unabsorbed photons back into the active silicon volume for a second absorption pass, thereby enhancing the sensor's infrared quantum efficiency.

This functional dual-purpose introduces a key engineering tradeoff: optimizing MET3 for low electrical resistance requires wide metal traces, whereas optimizing optical fill factor requires careful layout spacing to maximize planar reflective coverage while preventing unwanted optical diffraction and crosstalk into adjacent pixel storage nodes.

Walk the Real Module

To examine the operational sequence of the 40nm metal-three interconnect integration module, engineers can follow the detailed step-by-step interactive workflow. The flow starts with trench lithography on the planarized ILD2 substrate, followed by anisotropic oxide etching, wet clean, barrier/seed deposition, copper electroplating, and dual-step CMP planarization.

Open METAL 3 TRENCH - Photo in the interactive flow

This interactive resource allows process development engineers to evaluate causal relationships between unit process inputs and exit state deliverables, highlighting critical inspection points where barrier defects or dishing anomalies can propagate into downstream metallization modules.

Related Learning Paths

Engineers analyzing the MET3 integration sequence should review adjacent process modules that define its physical boundaries:

• The 40nm BSI CMOS Image Sensor process flow outlines the overall module architecture and integration strategy across the entire sensor flow.
• The 40nm BSI CMOS Image Sensor via-two integration process flow covers the vertical landing plugs that connect metal-two to metal-three.
• The 40nm BSI CMOS Image Sensor third interlayer dielectric integration process flow details the downstream dielectric module that isolates metal-three from metal-four.

Future Outlook

As BSI CMOS image sensor architectures transition toward fine-pitch 3D wafer stacking and sub-micron pixel dimensions, metal interconnect modules face aggressive scaling demands. In 3D-stacked image sensors, where the pixel array die is face-to-face bonded to a peripheral logic die, upper metal layers like MET3 participate in high-density inter-die communication or function as ground-shielding planes to suppress capacitive crosstalk between high-speed logic clocking and sensitive pixel column amplifiers.

To accommodate narrower metal pitches without incurring prohibitive RC delay penalties, ultra-low-k (ULK) dielectrics and thin ALD-based TaN/Mn-based self-forming diffusion barriers are being explored. Additionally, integrating deep trench isolation (DTI) structures and back-surface optical grids requires co-optimizing the MET3 metal profile to maintain high reflectivity without inducing mechanical stress-induced dark current degradation.