40nm BSI CMOS Image Sensor Via-Two Integration: Process Flow Principles and Device Physics

Role in the Complete Flow

The via-two (V2) module in a 40nm BSI CMOS Image Sensor serves as the critical inter-level bridging step between the second-level metal interconnect and the third-level metal that follows. In a backside-illuminated (BSI) CMOS image sensor architecture, the front-side metallization stack carries pixel readout signals, bias lines, and peripheral logic interconnects, all of which must be routed through successive via levels to reach bonding pads and external circuitry. The via-two module specifically receives the completed second interlayer dielectric (ILD2) stack with its planarized metal-two lines, and its downstream deliverable is a patterned and etched via cavity matrix integrated into a dual-damascene scheme that establishes reliable vertical electrical continuity to the metal-three level.

The 40nm via-two integration is not merely a mechanical connection step. In a BSI CMOS image sensor, the front-side metal stack also functions as an optical reflector layer that redirects unabsorbed photons back toward the photodiode array, boosting quantum efficiency. The via-two pattern density and geometry therefore influence both electrical parasitics and optical behavior. The V2 module must deliver low-resistance via contacts, minimal parasitic capacitance to adjacent metal layers, and a surface topography suitable for subsequent KrF lithography defined metal-three patterning. Any discontinuity, voiding, or misalignment introduced at this stage propagates through all subsequent interconnect layers and can degrade signal integrity along the pixel readout path.

For the broader 40nm BSI CMOS Image Sensor process flow, the V2 module sits at a juncture where interconnect complexity transitions from pixel-array-local routing to broader peripheral and column-parallel signal routing. The integration logic demands that the via-two layer maintains alignment fidelity to underlying metal-two features while providing a robust process window for the metal-three trench lithography that follows.

Entry State and Sequence Logic

Upstream Dependencies

The V2 module process flow begins after the second interlayer dielectric integration and chemical mechanical planarization (CMP) have produced a planarized surface above the metal-two conductors. The dielectric stack must exhibit low total thickness variation and minimal surface defect density, because the via-two lithography step relies on a shallow depth of focus inherent to scaled technology nodes. Any residual topography from the ILD2 CMP step directly narrows the focus budget for via-two patterning, which in turn affects via critical dimension (CD) uniformity across the wafer.

In the 40nm BSI CMOS Image Sensor, the entry state also includes the completed pinned photodiode (PPD) structures, transfer gates, and floating diffusion (FD) nodes in the underlying silicon device layer. The front-side interconnect stack built above these devices must not introduce stress or contamination that could alter the carefully engineered doping profiles of the PPD or FD regions. Prior process steps have already established the ion implantation and activation annealing sequences that define photodiode and FD electrical characteristics. The via-two integration must preserve these characteristics by avoiding excessive thermal budgets or plasma-induced damage during via etch.

Sequence Ordering Logic

The via-two integration principles dictate that the via-two lithography and etch steps occur prior to metal-three trench definition in a via-first dual-damascene process. Rather than filling and polishing the via separately as in a single-damascene scheme, via-two photolithography and plasma etching define the vertical cavities in the dielectric stack first, preparing the matrix for subsequent metal-three trench patterning before a single, combined barrier, seed, electroplated metal fill, and CMP sequence completes both inter-level features. This ordering ensures that the via plug is self-aligned to the overlying metal-three trench and underlying metal-two pad while simplifying CMP steps.

The integration logic for the 40nm BSI CMOS Image Sensor via-two integration requires careful coordination with the KrF lithography used for via patterning. The photoresist and underlying bottom anti-reflective coating (BARC) or hardmask stack must be selected to provide sufficient etch selectivity to the ILD material while maintaining the via CD control needed for reliable metallization.

Physical and Chemical Mechanisms

Via Patterning and Etch Chemistry

The via-two formation begins with the VIA 2 - Photo step using KrF optical lithography, where the photoresist is exposed through a reticle defining the via matrix. The photoactive compound in the resist undergoes a chemical transformation upon photon absorption, altering its solubility in the developer solution. To prevent pattern collapse induced by capillary forces during wet development of high-aspect-ratio features, exposure dose and focus depth are tightly coupled. Optical proximity correction (OPC) is applied to the reticle to counteract optical diffraction and proximity interference at dense via pitches.

The subsequent dielectric etch is an anisotropic reactive ion etching (RIE) process where fluorocarbon-based plasmas chemically react with the dielectric material while ion bombardment provides directional etching. The etch chemistry must achieve high selectivity to the underlying metal-two conductor to prevent excessive recessing or damage to the metal pad, which would elevate contact resistance or generate opens. The etch must also maintain vertical, smooth sidewall profiles to ensure uniform barrier deposition during downstream processing.

Dual-Damascene Metallization and CMP

Following via-two etching, resist strip, and subsequent metal-three trench lithography and etching, a conformal diffusion barrier layer—such as ALD or PVD TiN or TaN—lines the combined via and trench sidewalls. The barrier prevents copper or other conductive metals from migrating into the surrounding dielectric and underlying silicon, which is critical for maintaining dark current and low noise performance in the CMOS image sensor pixels. A thin seed layer is then deposited to provide a conductive nucleation surface for electroplating.

The metal fill process relies on electrochemical deposition, where metal ions from the plating bath are reduced at the cathodic wafer surface. Superfilling additives in the chemistry promote bottom-up fill within narrow via structures, suppressing keyhole void formation. Finally, chemical mechanical planarization removes overburden metal and barrier films, stopping on the upper dielectric to yield a planar surface for downstream metallization tiers.

Doping and Junction Integrity

In the 40nm BSI CMOS Image Sensor, via-two processing occurs well after the critical ion implantation and activation annealing steps that define the PPD and FD doping profiles. The thermal budget of the via-two module—including any post-metallization anneals—must be strictly constrained to prevent dopant redistribution in underlying junctions. High temperatures can cause dopant diffusion that broadens junction profiles and degrades the carefully engineered electric field distribution in the PPD.

The high-concentration p+ surface layer of the PPD creates a strong surface drift electric field that efficiently collects photogenerated carriers while passivating interface states at the Si–SiO₂ interface. Any thermal perturbation from the via-two module that alters this doping profile could degrade optical sensitivity and increase dark current. The integration logic therefore demands that the via-two thermal budget be minimized and that activation annealing for device implants remains strictly upstream.

Interfaces and Failure Propagation

Via-to-Metal Interface

The interface between the via-two plug and the underlying metal-two pad is a primary failure propagation site. Inadequate barrier coverage, clean residue, or interfacial oxide formation increases contact resistance, which directly degrades the conversion gain and readout noise of the CMOS image sensor. Conversion gain depends on the total capacitance at the FD node, and any additional parasitic resistance or RC delay in the readout path reduces signal bandwidth and increases temporal noise.

In a 40nm BSI CMOS Image Sensor, where the front-side metal stack also serves as an optical reflector, voiding or delamination at the via-to-metal interface can create localized optical scattering centers. This scattering reduces overall stack reflectivity and decreases quantum efficiency. The failure propagates directionally: higher via resistance leads to slower pixel readout, higher temporal noise, and a degraded signal-to-noise ratio under low-light conditions.

Via-to-ILD Interface

The via-two sidewall interface with the ILD material influences parasitic capacitance between adjacent via plugs and neighboring metal traces. In scaled technology nodes, reduced interconnect pitch increases capacitive coupling, which can cause crosstalk between pixel readout signal paths. While the BSI architecture moves the primary photodiode array to the wafer backside, front-side interconnect crosstalk remains a key concern for high-speed column-parallel readout architectures.

The dielectric constant and sidewall roughness of the etched via hole affect barrier layer conformality and effective via capacitance. Rough sidewalls can cause barrier thinning or local pinholes, creating pathways for metal diffusion into the ILD and eventually toward the active silicon substrate. Metal contamination in the silicon introduces generation-recombination centers in the PPD depletion region, directly elevating dark current and white pixel defect counts.

CMP and Topography Propagation

The dual-damascene CMP step that completes the via-two and metal-three level must remove overburden metal and barrier material while maintaining surface planarity. Dishing of wide metal features and dielectric erosion create localized topography variations that reduce the depth of focus margin for subsequent lithography steps. In the 40nm node, where optical focus budgets are constrained, topography excursions cause local CD variations that propagate as yield loss.

Downstream consequences of CMP non-uniformity include line width variation, sheet resistance drift, signal timing skew across the pixel array, and column-level fixed pattern noise (FPN). The integration tradeoff requires balancing CMP removal rates: aggressive polishing boosts throughput but risks dishing and erosion, whereas conservative polishing preserves planarity but risks leaving conductive metal residuals on the ILD surface, causing inter-line shorts.

Walk the Real Module

The interactive process flow provides a step-by-step walk through the 40nm BSI CMOS Image Sensor via-two integration. You can Open VIA 2 - Photo in the interactive flow to examine the exact sequence of operations within the V2 module process flow.

This step represents a critical juncture where the via-two photolithographic pattern is established prior to dielectric plasma etching. The preceding steps have established the second interlayer dielectric stack, while the following steps complete dielectric etching, metal-three trench patterning, dual-damascene metal fill, and CMP planarization. Understanding the state of the wafer at this specific step—including photoresist profile, focus depth margin, and overlay alignment—is essential for diagnosing yield-limiting defects in the via-two module.

For a broader view of where this module fits in the complete 40nm BSI CMOS Image Sensor process flow, the overall 40nm BSI CMOS Image Sensor process flow article provides the full integration context. The upstream 40nm BSI CMOS Image Sensor second interlayer dielectric integration process flow describes the ILD2 module that directly feeds into the via-two step, and the downstream 40nm BSI CMOS Image Sensor metal-three interconnect integration process flow covers the metal-three module that the via-two enables.

Backside-Illumination Specific Considerations

Backside Thinning Interaction

In backside-illuminated architectures, the semiconductor has to be thinned down so that most of the light can be absorbed within the depletion region [T2]. The front-side interconnect stack—including the via-two level—is completed before the wafer is flipped and bonded to a handle wafer for backside thinning. The backside thinning process uses mechanical grinding followed by selective wet etching to an etch stop layer, and the quality of this thinning step depends on the uniformity of the entire front-side stack. If the via-two module introduces significant thickness variation or stress, the backside thinning may produce non-uniform silicon thickness, which directly affects the optical path length and can cause pixel-to-pixel sensitivity variation.

The hybrid bonding of die-to-wafer type, used in some BSI CMOS image sensor architectures, requires that the front-side via and metal stack have low topography and robust mechanical integrity. Via-two voids or delamination can propagate during the bonding and thinning sequence, causing pixel-area defects that are only detectable at final wafer test, significantly reducing yield.

Packaging-Level Consequences

After the BSI CMOS image sensor die is completed, including all front-side interconnect levels, it is packaged with transparent substrates and molding compounds that form a hermetic seal around the pixel array. The via-two level, being an intermediate interconnect layer, contributes to the overall die-level stress distribution. Excessive metal density or non-uniform via distribution at the via-two level can create stress concentrations that lead to die cracking during packaging. The dam structures and molding process used in hermetic image sensor packaging are designed to accommodate the die's mechanical properties, but significant non-uniformity in the interconnect stack can exceed the stress tolerance of these structures.

Related Learning Paths

Engineers studying the via-two integration should also explore adjacent modules in the 40nm BSI CMOS Image Sensor interconnect stack. The 40nm BSI CMOS Image Sensor metal-three interconnect integration process flow directly follows the via-two module and depends on the surface quality it delivers. The 40nm BSI CMOS Image Sensor second interlayer dielectric integration process flow provides the upstream dielectric and metal-two structure that the via-two step connects to. For a complete view of all modules and their dependencies, the overarching 40nm BSI CMOS Image Sensor process flow article maps the entire integration sequence from device formation through final passivation.

Future Outlook

The via-two integration in 40nm BSI CMOS Image Sensors is evolving toward three-dimensional (3D) stacked architectures where the pixel array and readout circuitry are fabricated on separate wafers and bonded face-to-face. In 3D-stacked BSI CMOS image sensors, the traditional front-side via and interconnect stack may be replaced or augmented by through-silicon vias (TSVs) and hybrid bonding interfaces that connect the pixel die directly to the logic circuitry below. This trend reduces the number of conventional interconnect levels on the pixel die but increases the criticality of each remaining via level for signal routing between bonded tiers.

Additionally, the convergence of CMOS image sensors with microfluidic and lensless imaging platforms is pushing pixel sizes smaller and demanding even tighter via CD control. The via-two module will need to adopt advanced patterning techniques—including multi-exposure and self-aligned via approaches—to maintain yield at these scaled dimensions while preserving the low dark current and high quantum efficiency that define BSI CMOS image sensor performance.