40nm BSI CMOS Image Sensor Via-Two Integration: Process Flow Principles and Device Physics

Role in the Complete Flow

The via-two (V2) module in a 40nm BSI CMOS Image Sensor serves as the critical inter-level bridging step between the second-level metal interconnect and the third-level metal that follows [T1]. In a backside-illuminated (BSI) CMOS image sensor architecture, the front-side metallization stack carries pixel readout signals, bias lines, and peripheral logic interconnects, all of which must be routed through successive via levels to reach bonding pads and external circuitry [P2]. The via-two module specifically receives the completed second interlayer dielectric (ILD2) stack with its planarized metal-two lines, and its downstream deliverable is a patterned, etched, and filled via structure that establishes reliable electrical continuity to the metal-three level [T1].

The 40nm via-two integration is not merely a mechanical connection step [P4]. In a BSI CMOS image sensor, the front-side metal stack also functions as a reflector layer that redirects photons back toward the photodiode array, boosting quantum efficiency [P2]. The via-two pattern density and metal fill therefore influence both electrical parasitics and optical behavior [T1]. The V2 module must deliver low-resistance via contacts, minimal parasitic capacitance to adjacent metal layers, and a surface topography suitable for subsequent KrF lithography defined metal-three patterning (Engineering Practice). Any discontinuity, voiding, or misalignment introduced at this stage propagates through all subsequent interconnect layers and can degrade signal integrity at the pixel readout path [T1].

For the broader 40nm BSI CMOS Image Sensor process flow, the V2 module sits at a juncture where the interconnect complexity transitions from pixel-array-local routing to broader peripheral and column-parallel signal routing [P3]. The integration logic demands that the via-two layer maintains alignment fidelity to underlying metal-two features while providing sufficient process window for the metal-three lithography that follows [T1].

Entry State and Sequence Logic

Upstream Dependencies

The V2 module process flow begins after the second interlayer dielectric integration and chemical mechanical planarization (CMP) have produced a planarized surface exposing metal-two conductors [T1]. The dielectric stack must exhibit low total thickness variation and minimal surface defect density, because the via-two lithography step relies on a shallow depth of focus inherent to scaled technology nodes [T1]. Any residual topography from the ILD2 CMP step directly narrows the focus budget for via-two patterning, which in turn affects via critical dimension (CD) uniformity across the wafer [T1].

In the 40nm BSI CMOS Image Sensor, the entry state also includes the completed pinned photodiode (PPD) structures, transfer gates, and floating diffusion (FD) nodes in the underlying silicon device layer [P2]. The front-side interconnect stack built above these devices must not introduce stress or contamination that could alter the carefully engineered doping profiles of the PPD or FD regions [P1]. Prior process steps have already established the ion implantation and activation annealing sequences that define the photodiode and FD electrical characteristics [P1]. The via-two integration must preserve these characteristics by avoiding excessive thermal budgets or plasma-induced damage during via etch and barrier/seed deposition [P1].

Sequence Ordering Logic

The VIA 2 – Photo integration principles dictate that the via-two lithography and etch steps occur before the metal-two-to-metal-three continuous metal fill [A1]. This sequence follows a "via-first" integration approach where the via is patterned and etched into the ILD, then a barrier and seed layer are deposited, followed by metal fill and CMP [T1]. The ordering ensures that the via plug is self-aligned to the underlying metal-two pad and that the subsequent metal-three lithography can independently define the interconnect trace above [A1]. The sequence also allows the via-two etch chemistry to be optimized independently of the metal-three patterning requirements [T1].

The integration logic for the 40nm BSI CMOS Image Sensor via-two integration requires careful coordination with the KrF lithography used for via patterning [P4]. The photoresist and underlying hard mask stack must be selected to provide sufficient etch selectivity to the ILD material while maintaining the via CD control needed for reliable metal fill [T1].

Physical and Chemical Mechanisms

Via Patterning and Etch Chemistry

The via-two formation begins with KrF lithography, where the photoresist is exposed through a reticle defining the via pattern (Engineering Practice). The photoactive compound in the resist undergoes a chemical transformation upon photon absorption, altering its solubility in the developer solution [P1]. The exposed (or unexposed, depending on tone) regions are selectively removed, leaving a patterned resist mask on the ILD surface [T1].

The subsequent dielectric etch is a reactive ion etching (RIE) process where fluorocarbon-based plasmas chemically react with the dielectric material while ion bombardment provides directional etching [A1]. The etch chemistry must achieve high selectivity to the underlying metal-two conductor to prevent over-etching into the metal pad, which would increase via resistance and potentially create opens [T1]. The etch also must maintain vertical sidewall profiles to ensure uniform metal fill and avoid keyhole voids during subsequent deposition steps (Engineering Practice).

Barrier, Seed, and Metal Fill

After via etch and resist strip, a barrier layer—typically deposited by atomic layer deposition (ALD) or physical vapor deposition (PVD)—lines the via sidewalls and bottom [T1]. The barrier prevents metal diffusion into the surrounding dielectric and underlying silicon, which is critical for maintaining the dark current and noise performance of the CMOS image sensor pixels [P1]. A seed layer is then deposited to provide a conductive nucleation surface for the electroplated metal fill [A2].

The metal fill process relies on electrochemical deposition, where metal ions from the plating solution are reduced at the cathodic wafer surface [T1]. The mechanism follows Faraday's law of electrolysis, where the deposited mass is proportional to the total charge passed (Engineering Practice). The fill must be void-free and provide bottom-up filling within narrow via structures, which depends on the competition between conformal deposition and superfilling additives in the plating chemistry (Engineering Practice). Incomplete fill leads to elevated via resistance or open circuits, while overfill complicates the CMP planarization step [T1].

Doping and Junction Integrity

In the 40nm BSI CMOS Image Sensor, the via-two integration occurs after the critical ion implantation and activation annealing steps that define the PPD and FD doping profiles [P1]. The thermal budget of the via-two module—including any post-metal deposition anneal—must be constrained to prevent dopant redistribution in the underlying junctions [T1]. As described by the Fermi–Dirac distribution and intrinsic carrier concentration relationships, elevated temperatures increase intrinsic carrier concentration and can broaden junction profiles, degrading the carefully engineered electric field distribution in the PPD [T1][T2].

The high-concentration p+ surface layer of the PPD creates a strong surface drift electric field that efficiently collects UV-generated carriers, while passivating interface states at the Si–SiO₂ interface [P1]. Any thermal perturbation from the via-two module that alters this doping profile could degrade UV sensitivity and increase dark current [P1]. The integration logic therefore demands that the via-two thermal budget be minimized and that any activation annealing for upstream implants be completed before the interconnect stack is built [P1].

Interfaces and Failure Propagation

Via-to-Metal Interface

The interface between the via-two plug and the underlying metal-two pad is a primary failure propagation site (Engineering Practice). Inadequate barrier coverage or contamination at this interface increases contact resistance, which directly degrades the conversion gain and readout noise of the CMOS image sensor [P1][P3]. The conversion gain depends on the total capacitance at the FD node, and any additional parasitic resistance or capacitance from poor via contacts adds to the readout path impedance, reducing signal bandwidth and increasing temporal noise [P2].

In the 40nm BSI CMOS Image Sensor, where the front-side metal stack also serves as an optical reflector [P2], any voiding or delamination at the via-to-metal interface can create scattering centers that reduce the reflectivity and hence the quantum efficiency. The failure propagates directionally: a via resistance increase → slower pixel readout → higher readout noise → degraded signal-to-noise ratio under low-light conditions [P3].

Via-to-ILD Interface

The via-two sidewall interface with the ILD material influences parasitic capacitance between adjacent via plugs and between the via and surrounding metal lines [T1]. In scaled nodes, the reduced spacing between interconnects increases capacitive coupling, which can cause crosstalk between pixel signal paths [P2]. The BSI architecture partially mitigates this by moving the photodiode array to the backside, but the front-side interconnect crosstalk remains a concern for high-speed column-parallel readout [P3].

The dielectric constant and sidewall roughness of the etched via hole affect the barrier layer conformality and the effective capacitance of the via structure [P1]. Rough sidewalls can cause barrier thinning or pinholes, creating pathways for metal diffusion into the ILD and eventually into the underlying silicon device region [T1]. This diffusion is particularly damaging in a CMOS image sensor because it can introduce generation–recombination centers in the PPD depletion region, increasing dark current [P1][P2].

CMP and Topography Propagation

The via-two CMP step must remove the overburden metal and barrier material while planarizing the surface for the metal-three lithography (Engineering Practice). Dishing and erosion during CMP create localized topography variations that reduce the depth of focus margin for the subsequent KrF lithography step [T1]. In the 40nm node, where the focus budget is already constrained, even small topography excursions can cause via CD variation that propagates as yield loss [P1].

Downstream consequences of CMP non-uniformity include: metal-three line width variation → inconsistent sheet resistance → signal timing skew across the pixel array → column-level fixed pattern noise (FPN) [P3]. The directional tradeoff is that aggressive CMP removal rates improve throughput but increase dishing and erosion, while conservative removal rates improve planarity but risk metal residual left on the ILD surface, creating short circuits between adjacent metal-three features (Engineering Practice).

Walk the Real Module

The interactive process flow provides a step-by-step walk through the 40nm BSI CMOS Image Sensor via-two integration [P3]. You can Open V2 Step 180 in the interactive flow to examine the exact sequence of operations within the V2 module process flow (Engineering Practice).

This step represents a critical juncture where the via-two etch has been completed and the barrier/seed deposition is about to commence (Engineering Practice). The preceding steps have established the KrF lithography pattern and dielectric etch that define the via geometry, while the following steps complete the metal fill and CMP planarization [A2]. Understanding the state of the wafer at this specific step— including the via profile, etch residue cleanliness, and underlying metal-two exposure— is essential for diagnosing yield-limiting defects in the via-two module [T1].

For a broader view of where this module fits in the complete 40nm BSI CMOS Image Sensor process flow, the overall 40nm BSI CMOS Image Sensor process flow article provides the full integration context [P4]. The upstream 40nm BSI CMOS Image Sensor second interlayer dielectric integration process flow describes the ILD2 module that directly feeds into the via-two step, and the downstream 40nm BSI CMOS Image Sensor metal-three interconnect integration process flow covers the metal-three module that the via-two enables [P1].

Interfaces and Failure Propagation: BSI-Specific Considerations

Backside Thinning Interaction

In the BSI CMOS image sensor, the front-side interconnect stack—including the via-two level—is completed before the wafer is flipped and bonded to a handle wafer for backside thinning [A1]. The backside thinning process uses mechanical grinding followed by selective wet etching to an etch stop layer, and the quality of this thinning step depends on the uniformity of the entire front-side stack [A1]. If the via-two module introduces significant thickness variation or stress, the backside thinning may produce non-uniform silicon thickness, which directly affects the optical path length and can cause pixel-to-pixel sensitivity variation [A2].

The hybrid bonding of die-to-wafer type, used in some BSI CMOS image sensor architectures, requires that the front-side via and metal stack have low topography and robust mechanical integrity [A1]. Via-two voids or delamination can propagate during the bonding and thinning sequence, causing pixel-area defects that are only detectable at final wafer test, significantly reducing yield [A1].

Packaging-Level Consequences

After the BSI CMOS image sensor die is completed, including all front-side interconnect levels, it is packaged with transparent substrates and molding compounds that form a hermetic seal around the pixel array [A2]. The via-two level, being an intermediate interconnect layer, contributes to the overall die-level stress distribution [T1]. Excessive metal density or non-uniform via distribution at the via-two level can create stress concentrations that lead to die cracking during packaging [A2]. The dam structures and molding process used in hermetic image sensor packaging are designed to accommodate the die's mechanical properties, but significant non-uniformity in the interconnect stack can exceed the stress tolerance of these structures [A2].

Related Learning Paths

Engineers studying the via-two integration should also explore adjacent modules in the 40nm BSI CMOS Image Sensor interconnect stack [P3]. The 40nm BSI CMOS Image Sensor metal-three interconnect integration process flow directly follows the via-two module and depends on the surface quality it delivers [P1]. The 40nm BSI CMOS Image Sensor second interlayer dielectric integration process flow provides the upstream dielectric and metal-two structure that the via-two step connects to [P1]. For a complete view of all modules and their dependencies, the overarching 40nm BSI CMOS Image Sensor process flow article maps the entire integration sequence from device formation through final passivation [P3].

Future Outlook

The via-two integration in 40nm BSI CMOS Image Sensors is evolving toward three-dimensional (3D) stacked architectures where the pixel array and readout circuitry are fabricated on separate wafers and bonded face-to-face [P4]. In 3D-stacked BSI CMOS image sensors, the traditional front-side via and interconnect stack may be replaced or augmented by through-silicon vias (TSVs) and hybrid bonding interfaces that connect the pixel die directly to the logic circuitry below [A1][A4]. This trend reduces the number of conventional interconnect levels on the pixel die but increases the criticality of each remaining via level for signal routing between bonded tiers [T1].

Additionally, the convergence of CMOS image sensors with microfluidic and lensless imaging platforms is pushing pixel sizes smaller and demanding even tighter via CD control [P4]. The via-two module will need to adopt advanced patterning techniques—including multi-exposure and self-aligned via approaches—to maintain yield at these scaled dimensions while preserving the low dark current and high quantum efficiency that define BSI CMOS image sensor performance [P2][P4].