40nm BSI CMOS Image Sensor Metal-Two Interconnect Integration: Process Flow Principles and Device Physics

Role in the Complete Flow

The metal-two (MET2) interconnect module in a 40nm BSI CMOS Image Sensor sits at a critical juncture in the frontside metallization sequence, receiving the patterned metal-one layer, its overlying interlayer dielectric (ILD2), and pre-etched via-one (V1) cavities as input. At this stage, the wafer has already completed transistor formation, pinned photodiode (PPD) integration, first-level metal patterning, and initial via etching — all of which establish the photosensitive core and readout circuit foundation of the sensor. The MET2 module must deliver a robust, low-resistance second metal routing layer that connects pixel readout nodes to peripheral column circuitry and, ultimately, to the logic and analog signal chain.

In backside-illuminated architectures, light enters from the thinned rear substrate surface to avoid absorption by frontside gate and metal layers [T2]. On the frontside, metallization serves a dual purpose: it provides electrical interconnect functionality and simultaneously acts as an optical reflector layer that can boost quantum efficiency (QE) by reflecting transmitted photons back toward the photodiode. This means the MET2 layer is not merely an electrical conductor — its topology, coverage, and material reflectivity directly influence the optical path length and carrier collection probability. The 40nm metal-two interconnect integration must therefore balance electrical routing density with optical transparency or reflectivity considerations, depending on the pixel design strategy.

Prior to MET2 trench patterning, via-one (V1) etching is completed in the interlayer dielectric, establishing a via-first dual-damascene scheme before downstream modules proceed to ILD3 deposition and higher metal levels. Connections between two levels of interconnects are formed as vias through openings in intermetal dielectric layers [T1]. The integrity of MET2 directly determines whether via landing is reliable, whether crosstalk between adjacent routing lines stays within acceptable limits, and whether the planarization quality is sufficient for optical lithography depth of field in subsequent patterning steps. The 40nm BSI CMOS Image Sensor Process Flow depends on MET2 as a structural anchor point for all upper-level interconnect and passivation modules.

Entry State and Sequence Logic

Upstream Dependencies

When the MET2 module begins, the wafer carries a fully patterned metal-one layer embedded within ILD1, covered by ILD2, into which V1 via holes have already been etched. The surface topography at this point is inherently complex and non-planar — a consequence of the pre-existing via cavities and underlying metal topography. The ILD2 layer and via fill preparation must provide adequate planarization before MET2 trench patterning can proceed. The 40nm BSI CMOS Image Sensor Second Interlayer Dielectric Integration directly governs the quality of this entry dielectric surface.

The sequence logic is tightly coupled: because the pre-etched vias present severe local topography, a sacrificial gap-fill material or bottom anti-reflective coating (BARC) is spin-coated to fill the vias and planarize the surface prior to photoresist coating. If the gap-fill treatment fails to produce a sufficiently planar surface, the MET2 trench photo step will suffer from depth-of-focus variation across the exposure field, leading to critical dimension (CD) variation and potential metal stringers or opens. The 40nm BSI CMOS Image Sensor Via-One Integration provides the pre-etched via context that MET2 trench patterning must overlay cleanly.

Downstream Deliverables

The MET2 module must deliver:

• A patterned metal layer with reliable electrical continuity across both pixel array and peripheral logic regions
• A filled dual-damascene structure where MET2 trenches seamlessly merge with underlying V1 vias
• A top surface sufficiently planarized by chemical mechanical planarization (CMP) to support subsequent ILD3 deposition
• An optical stack configuration that maintains QE without introducing specular reflections that cause pixel crosstalk

The 40nm BSI CMOS Image Sensor Metal-Three Interconnect Integration is a direct downstream consumer of MET2 completion quality. Any residual metal overburden, severe dishing, or dielectric erosion in MET2 will propagate as focus and etching defects in upper interconnect levels.

Physical and Chemical Mechanisms

METAL 2 TRENCH - Photo Integration Principles

The METAL 2 TRENCH - Photo step is the defining lithographic operation in the MET2 module process flow. At the 40nm node, optical lithography is typically employed for metal trench patterning. The fundamental challenge lies in resolving narrow metal trenches with straight sidewalls over a planarized gap-fill coating while ensuring precise overlay alignment with pre-existing V1 vias.

The physical mechanism begins with spin-coating photoresist over the planarized gap-fill/BARC stack. During optical exposure, light passes through the photomask to chemically alter the resist, but systematic distortions from optical interference must be countered using advanced optical proximity correction (OPC) techniques. Following exposure, the development process removes the soluble resist regions, leaving a physical trench mask directly aligned over the filled vias.

Trench Etch and Metal Fill Chemistry

After lithography, the trench pattern is transferred through the ILD2 dielectric using a fluorine-based plasma etch chemistry. The etch must achieve anisotropic profiles with vertical sidewalls and clean stopping on the dielectric barrier or lower etch-stop layer. After dry etching, ashing and wet cleaning remove the remaining photoresist and sacrificial gap-fill material from inside the vias, exposing the underlying metal-one landing surface.

Metal deposition follows, beginning with a physical vapor deposition (PVD) tantalum/tantalum nitride (Ta/TaN) barrier liner, followed by a thin copper seed layer. The Ta/TaN barrier prevents copper diffusion into surrounding dielectrics — a critical requirement in CMOS image sensors where metallic contamination in the photodiode region creates deep-level traps that increase dark current and white pixel defect density. The PVD barrier must deliver conformal step coverage along both trench sidewalls and via sidewalls; localized liner thinning creates diffusion pathways that cause early dielectric breakdown.

Electrochemical plating (ECP) fills the dual-damascene structure with bulk copper. The plating bath utilizes organic additives (accelerators, suppressors, levelers) to induce bottom-up fill, driving preferential deposition at the via bottom and trench floor before sidewall pinch-off can occur. This mechanism prevents void formation in high-aspect-ratio via-trench structures.

CMP Planarization Physics

Chemical mechanical planarization is executed in sequence: copper CMP removes overburden copper, followed by barrier CMP to polish away the Ta/TaN liner on the field oxide, leaving isolated metal lines strictly inside the trenches. The polishing process combines chemical oxidation of the metal surface with mechanical abrasion by silica-based slurry particles under localized polishing pressure. However, CMP inevitably causes dishing (recess of wide metal lines) and erosion (dielectric thinning in dense line arrays), both of which must be constrained within strict windows to maintain downstream focus budgets.

Interfaces and Failure Propagation

MET2-to-ILD2 Interface

The interface between the Ta/TaN barrier liner and the underlying ILD2 dielectric oxide represents a primary mechanical failure pathway. Inadequate pre-metal-deposition degas or residual chemical contamination weakens interfacial adhesion, leading to barrier delamination during thermal cycling or mechanical stress. Delamination manifests as line peeling, intermittent open circuits, or localized resistance drift.

Metal Diffusion into Photodiode Region

In BSI sensors, the active photodiode is located in the silicon substrate directly beneath the frontside metallization stack. Copper atoms from MET2 can migrate through micro-voids or grain boundaries in a compromised barrier layer. Once copper reaches the photodiode depletion region, it forms deep-level recombination centers in the silicon bandgap, causing severe dark current degradation and white pixel defects. While proximity gettering techniques (such as hydrocarbon ion implantation) provide a statistical trap for migrating metallic impurities, a continuous, pinhole-free MET2 barrier layer remains the primary defense.

Overlay Misalignment and Via Chamfering

Because the V1 vias are etched prior to the MET2 trench photo step, overlay accuracy between the trench mask and the underlying via is paramount. Misalignment between the MET2 trench and pre-existing V1 via leads to via chamfering during trench etching, where the etch plasma clips the upper corner of the via hole. Via chamfering alters via geometry, increases parasitic capacitance, and introduces high via contact resistance variance.

Crosstalk and Optical Interaction

Frontside metal lines in BSI sensors reflect unabsorbed light back into the silicon substrate, which can constructively enhance QE for targeted optical paths. However, overly wide MET2 lines or high metal density in the pixel array block or scatter light entering from adjacent angles, increasing optical crosstalk between neighboring pixels. Designing the MET2 routing grid requires co-optimizing electrical IR drop against pixel optical chief ray angle (CRA) tolerance.

Thermal Budget and Barrier Integrity

Subsequent BEOL operations — including ILD3 deposition, V2 via processing, and higher metal layers — subject MET2 to cumulative thermal stress. Exceeding the thermal stability window of the Ta/TaN liner and copper grain structure drives copper grain growth, stress-induced voiding, and electromigration degradation at via landing interfaces.

Walk the Real Module

To see the exact MET2 module sequence in the context of the full 40nm BSI CMOS Image Sensor process, you can Open METAL 2 TRENCH - Photo in the interactive flow. This step represents the lithographic initiation point where gap-fill planarization, optical proximity correction, and trench patterning converge prior to dielectric etch, barrier deposition, copper fill, and CMP.

The interactive flow illustrates how the MET2 module integrates with upstream V1 via etching and downstream ILD3 deposition, providing a visual map of process dependencies. By inspecting the step sequence, process engineers can trace how lithographic overlay, liner conformality, or CMP polishing variation at MET2 influences final sensor yield and reliability.

Related Learning Paths

To build a comprehensive understanding of the 40nm BSI CMOS Image Sensor interconnect architecture, explore these adjacent integration modules:

• The 40nm BSI CMOS Image Sensor Process Flow article outlines the complete fabrication sequence from substrate preparation through backside thinning and optical stack completion.
• The 40nm BSI CMOS Image Sensor Second Interlayer Dielectric Integration article covers the deposition and planarization physics establishing the MET2 entry surface.
• The 40nm BSI CMOS Image Sensor Via-One Integration article details the via-first etching process that creates the pre-existing via topography filled during MET2 integration.
• The 40nm BSI CMOS Image Sensor Metal-Three Interconnect Integration article explains how downstream metal modules inherit the surface topography and thermal budget delivered by MET2.

Future Outlook

The evolution of CMOS image sensor interconnects is driven by multi-wafer 3D integration and architectural scaling. In advanced 3D-stacked CIS architectures, pixel arrays and peripheral logic circuits are processed on separate wafers and joined via direct bond interconnects. This separation reduces frontside routing density on the pixel wafer, allowing MET2 to focus strictly on local pixel interconnects while long-distance signal routing is shifted to the logic tier.

Second, Buried interconnect structures place conductive lines under the silicon surface, isolated from the substrate by dielectrics [A1]. Integrating subterranean interconnect channels within shallow trench regions could complement or partially replace surface MET2 lines, freeing frontside area and reducing optical reflection interference in BSI pixels.

Finally, as interconnect pitches continue to shrink, the integration of ultra-low-k dielectrics and ultra-thin conformal barrier liners will require rigorous thermal budget engineering to suppress dark current generation while preserving high-frequency pixel readout speeds.