40nm BSI CMOS Image Sensor Metal-Two Interconnect Integration: Process Flow Principles and Device Physics

Role in the Complete Flow

The metal-two (MET2) interconnect module in a 40nm BSI CMOS Image Sensor sits at a critical juncture in the frontside metallization sequence, receiving the patterned metal-one layer and its overlying interlayer dielectric stack as input [A2]. At this stage, the wafer has already undergone transistor formation, pinned photodiode (PPD) integration, and first-level metal patterning — all of which define the photosensitive and readout circuit foundation of the sensor [P2]. The MET2 module must deliver a robust, low-resistance second metal routing layer that connects pixel readout nodes to peripheral column circuitry and, ultimately, to the logic and analog signal chain [A1].

In a backside-illuminated (BSI) architecture, the frontside metallization serves a dual purpose: it provides electrical interconnect functionality and simultaneously acts as an optical reflector layer that can boost quantum efficiency (QE) by reflecting transmitted photons back toward the photodiode [P2]. This means the MET2 layer is not merely an electrical conductor — its topology, coverage, and material reflectivity directly influence the optical path length and carrier collection probability [T1]. The 40nm metal-two interconnect integration must therefore balance electrical routing density with optical transparency or reflectivity considerations, depending on the pixel design strategy [A1].

Downstream of MET2, subsequent modules include via-one (V1) formation, additional interlayer dielectric (ILD) deposition, and higher metal levels that route signals off the pixel array to bonding pads and peripheral I/O [T1]. The integrity of MET2 directly determines whether via landing is reliable, whether crosstalk between adjacent routing lines stays within acceptable limits, and whether the planarization quality is sufficient for KrF lithography depth of field in subsequent patterning steps [T1]. The 40nm BSI CMOS Image Sensor process flow depends on MET2 as a structural anchor point for all upper-level interconnect and passivation modules [P1].

Entry State and Sequence Logic

Upstream Dependencies

When the MET2 module begins, the wafer carries a fully patterned metal-one layer embedded within the first interlayer dielectric [A1]. The surface topography at this point is inherently non-planar — a consequence of the multiple deposition, etch, and patterning cycles that have preceded this step [T1]. The ILD2 layer, deposited above metal-one, must provide adequate planarization before MET2 patterning can proceed [A1]. The 40nm BSI CMOS Image Sensor second interlayer dielectric integration directly governs the quality of this entry surface [P1].

The sequence logic is tightly coupled: if the ILD2 surface is insufficiently planarized, the MET2 trench photo step will suffer from depth-of-focus variation across the exposure field, leading to critical dimension (CD) variation and potential metal stringers or opens [P1]. This is particularly acute in CMOS image sensors, where the pixel array region has a highly regular but dense routing pattern, while the peripheral region contains larger logic-style interconnects — two regions with very different topographic profiles on the same wafer [T1].

Downstream Deliverables

The MET2 module must deliver:

• A patterned metal layer with reliable electrical continuity across both pixel and peripheral regions
• A surface sufficiently planar for the subsequent V1 via formation and ILD3 deposition
• Metal lines with sidewall profiles that support reliable via landing in the next module
• An optical stack configuration that does not degrade QE or introduce specular reflections that cause optical crosstalk [P2]

The 40nm BSI CMOS Image Sensor via-one integration is the immediate downstream consumer of MET2 output quality. Any sidewall roughness, metal erosion, or dishing from chemical mechanical planarization (CMP) in MET2 will propagate as via landing variation and contact resistance spread in V1 [P4].

Physical and Chemical Mechanisms

METAL 2 TRENCH - Photo Integration Principles

The METAL 2 TRENCH - Photo step is the defining lithographic operation in the MET2 module process flow [A1]. At the 40nm node, KrF lithography is typically employed for metal trench patterning (Engineering Practice). The fundamental challenge lies in resolving narrow metal trenches with straight sidewalls over a non-planar underlying topography while maintaining CD uniformity across the full field [A1].

The physical mechanism begins with photoresist application on the planarized ILD2 surface [P2]. The resist must exhibit sufficient contrast and etch resistance to withstand the subsequent dry etch that transfers the trench pattern into the underlying dielectric and metal stack [A1]. The exposure process relies on the optical projection system's ability to form aerial images with adequate modulation transfer function at the target dimensions — a function of illumination aperture settings, phase-shift mask design, and resist process optimization (Engineering Practice).

Trench Etch and Metal Fill Chemistry

After lithography, the trench pattern is transferred through the dielectric barrier and etch-stop layers using a fluorine-based plasma etch chemistry [A1]. The etch must achieve anisotropic profiles — vertical sidewalls with minimal undercut — because any lateral etch will widen the trench beyond the designed CD and compromise the metal line pitch [A1]. The etch chemistry must also demonstrate high selectivity to the underlying metal-one layer, ensuring the etch stops cleanly without damaging the first-level interconnect [T1].

Metal deposition follows, typically using a physical vapor deposition (PVD) tantalum/tantalum nitride (Ta/TaN) barrier layer followed by a copper seed layer and electrochemical plating (ECP) fill [T1]. The barrier layer prevents copper diffusion into surrounding dielectrics — a critical requirement in CMOS image sensors where metallic contamination in the photodiode region can create deep-level traps that increase dark current and white pixel defects [P4]. The PVD barrier must provide conformal step coverage along trench sidewalls and bottoms; insufficient coverage leads to copper diffusion pathways and premature dielectric breakdown [A1].

The ECP fill mechanism relies on electrolytic reduction of copper ions from a plating bath onto the conductive seed layer (Engineering Practice). The plating must achieve bottom-up fill — preferential deposition at the trench bottom before sidewall closure — to avoid void formation in narrow trenches [A1]. This is governed by the interaction of plating bath additive chemistry (accelerators, suppressors, levelers) with the evolving copper surface, creating differential deposition rates that favor void-free fill (Engineering Practice).

CMP Planarization Physics

Chemical mechanical planarization removes the overburden copper and barrier material, leaving metal only within the trenches (Engineering Practice). The mechanism involves simultaneous chemical oxidation of the copper surface and mechanical abrasion by silica-based slurry particles (Engineering Practice). The polish rate depends on the local pressure — higher features experience greater pressure and polish faster, enabling global planarization (Engineering Practice). However, CMP introduces dishing (recess of wide metal lines) and erosion (thinning of dielectric in dense regions), both of which must be controlled within tight windows to maintain downstream lithography focus budgets [T1].

Interfaces and Failure Propagation

MET2-to-ILD2 Interface

The interface between MET2 metal lines and the underlying ILD2 dielectric is a primary failure propagation pathway [P3]. Poor adhesion between the TaN barrier and the ILD2 oxide can lead to metal delamination during thermal cycling, creating open circuits or intermittent resistance drift [P3]. The adhesion quality depends on the ILD2 surface preparation — residual organic contamination or moisture from incomplete pre-metal-deposition baking will weaken the barrier-to-dielectric bond [T1].

Metal Diffusion into Photodiode Region

In a BSI CMOS image sensor, the photodiode is formed in the silicon substrate beneath the frontside interconnect stack [P1]. Copper atoms from MET2 can diffuse through barrier defects or along ILD2 grain boundaries, eventually reaching the photodiode depletion region [P1]. Once there, they form deep energy level defects in the silicon bandgap, acting as generation-recombination centers that increase dark current and degrade white pixel defect density [P4]. The proximity gettering techniques described in the literature — including hydrocarbon molecular ion implantation — are specifically deployed to capture such metallic impurities before they reach the device active region [P4]. However, gettering is a statistical defense, not an absolute barrier; the quality of the MET2 barrier layer remains the primary prevention mechanism (Engineering Practice).

CMP-Induced Topography and Downstream Via Landing

Dishing of wide MET2 lines and erosion of dielectric between dense lines create local height variations that propagate into the V1 via module [T1]. When the via-one trench is etched, a via landing on a dished metal surface may encounter insufficient metal thickness, leading to high via contact resistance or an open [A1]. Conversely, erosion of the dielectric in dense regions may cause the via etch to break through prematurely, creating short circuits to underlying MET2 lines [T1]. The interaction is directional: wider MET2 lines dish more, denser regions erode more, and the V1 module inherits both effects simultaneously [P4].

Crosstalk and Optical Interaction

In BSI sensors, the frontside metal stack — including MET2 — is positioned between the photodiode and the backside illumination surface after substrate thinning [A2]. Metal lines can reflect photons back into the silicon, increasing the effective optical path and boosting QE for certain geometries [P2]. However, if MET2 routing density is too high or lines are too wide in the pixel region, the metal can block the optical path from the backside, reducing fill factor and increasing optical crosstalk between adjacent pixels [P1]. The tradeoff is directional: more metal routing improves electrical performance but degrades optical performance, and vice versa [P3]. Stacked sensor designs with interposed shielding layers can partially mitigate this tradeoff by providing dedicated electromagnetic isolation between pixel and logic tiers [A2].

Thermal Budget and Barrier Integrity

The MET2 module must withstand all subsequent thermal processes — including ILD3 deposition, via formation, and higher metal-level processing — without barrier degradation or copper hillock formation [T1]. Any thermal treatment applied after MET2 completion can drive copper grain growth, stress migration, or barrier diffusion if the thermal budget exceeds the stability window of the Ta/TaN barrier and copper microstructure [P3]. The directionality is clear: higher post-MET2 thermal budgets increase the risk of electromigration and stress-induced voiding, particularly at via landing sites where current density is highest [P3].

Walk the Real Module

To see the exact MET2 module sequence in the context of the full 40nm BSI CMOS Image Sensor process, you can Open MET2 Step 168 in the interactive flow [T1]. This step represents the integration point where the MET2 trench photo, etch, metal fill, and CMP operations converge to produce the second-level interconnect [A1].

The interactive flow illustrates how the MET2 module connects to upstream ILD2 planarization and downstream V1 via formation, providing a visual map of the integration dependencies discussed throughout this article (Engineering Practice). By examining the step sequence, engineers can trace how a defect or process variation at any MET2 sub-step propagates through the remaining flow — from ILD3 deposition through final passivation and bonding pad opening [T1].

Related Learning Paths

For engineers seeking to deepen their understanding of the 40nm BSI CMOS Image Sensor interconnect ecosystem, several adjacent topics provide complementary context:

• The 40nm BSI CMOS Image Sensor process flow article provides the full-module overview, showing how MET2 fits within the complete fabrication sequence from substrate preparation through backside thinning [P1].
• The 40nm BSI CMOS Image Sensor second interlayer dielectric integration article details the planarization chemistry and deposition physics that directly determine the MET2 entry surface quality [P1].
• The 40nm BSI CMOS Image Sensor via-one integration article explains how V1 landing physics inherit the topographic and metallurgical state delivered by MET2 completion [P1].

These articles together form a connected learning cluster covering the interconnect integration chain from metal-one through via-one, with MET2 as the central structural and electrical bridge [A1].

Future Outlook

The evolution of CMOS image sensor interconnect integration is driven by several converging trends [A2]. First, three-dimensional stacking — where pixel array and logic chips are fabricated separately and bonded via through-silicon vias (TSVs) — is reshaping the role of frontside metal layers [A2]. In stacked architectures, MET2 may serve less as a signal routing layer and more as a localized pixel interconnect, with global routing moved to the logic tier [A2]. This reduces frontside metal density and can improve optical fill factor in BSI designs [P4].

Second, buried interconnect structures — where conductive lines are placed below the silicon surface within shallow trench isolation regions — offer a path to increase integration density without consuming surface routing area [A1]. Such underground interconnects could partially replace or complement traditional MET2 routing, though they introduce significant process complexity in narrow trench fill and barrier integrity [A1].

Third, proximity gettering technologies using hydrocarbon molecular ion implantation are becoming essential as thermal budgets shrink and metallic contamination tolerance tightens in advanced CIS nodes [P4]. As MET2 barrier layers become thinner and more conformal at advanced nodes, the role of gettering as a secondary defense against copper diffusion into the photodiode region will grow [P3].

Finally, the continuing push for higher conversion gain and wider dynamic range in CMOS image sensors [P1] places indirect pressure on MET2 design: lower parasitic capacitance in the floating diffusion readout path demands tighter control of metal-to-substrate and metal-to-metal coupling, making MET2 line placement and ILD dielectric constant increasingly critical parameters in the overall sensor optimization.