40nm BSI CMOS Image Sensor Via-One Integration: Process Flow Principles and Device Physics

Role in the Complete Flow

In the 40nm BSI CMOS Image Sensor process flow, the via-one (V1) integration module serves as the first inter-metal vertical interconnect opening layer within the back-end-of-line (BEOL) stack. Positioned directly above the first metal layer (M1), the V1 module defines and etches patterned vertical via holes through the dielectric stack—comprising a silicon carbonitride (ILD 1-1 SiCN) etch-stop liner and an inter-metal oxide layer (ILD 1-2) deposited over M1—to expose lower conductor landing pads for subsequent connection to the second metal layer (M2). Vertical via structures extend vertically between first and second metallization layers to establish electrical connections across the interconnect network [A1].

In backside illumination architectures, light enters from the substrate back to avoid photon absorption by front-side gate structures and metal layers [T2]. Although primary optical sensing occurs from the back, the front-side metallization stack—starting with M1 and V1—still influences overall sensor performance. Front-side metal lines can act as internal optical reflectors that redirect transmitted longer-wavelength photons back toward the photodiode to increase quantum efficiency. Consequently, the pattern density, spatial placement, and surface planarity of V1 structures carry both electrical routing implications and optical reflection considerations. The V1 module receives an inter-metal dielectric stack covering M1 and delivers a clean, precisely patterned and etched via hole array ready for downstream dual-damascene trench etching and metal fill.

For context on the dielectric preparation preceding vertical interconnect patterning, see the 40nm BSI CMOS Image Sensor first interlayer dielectric integration process flow.

Entry State and Sequence Logic

Upstream Dependencies

The V1 module enters after front-end-of-line (FEOL) device formation, contact plug deposition, M1 metallization, and inter-metal dielectric deposition (ILD 1-1 SiCN etch-stop and ILD 1-2 oxide) are complete. The pinned photodiodes, transfer gates, floating diffusions, and pixel readout transistors are already fully formed and protected beneath dielectric and metallization stacks.

Before photolithography begins, pre-lithography cleaning ensures that the underlying dielectric surface is free of particles and chemical contaminants. This cleaning step is vital because surface irregularities or organic residues can distort the local depth of focus during exposure or impede photoresist adhesion across the wafer.

Downstream Deliverables

Upon completion, the V1 module delivers a clean, fully opened via hole array through the ILD1 dielectric layers, exposing M1 landing pads for subsequent dual-damascene trench patterning and metal fill. Misalignment, incomplete etching, or unremoved etch polymers in V1 directly cause electrical open circuits, elevated contact resistance, or increased RC delay in pixel column readout buses. The 40nm BSI CMOS Image Sensor metal-two interconnect integration process flow builds directly upon the opened V1 via array.

Physical and Chemical Mechanisms

VIA 1 — Photo Integration Principles

The V1 module process flow begins with surface cleaning and photolithography. An anti-reflective coating is applied beneath the photoresist layer to suppress thin-film interference and standing wave effects caused by optical reflections off underlying M1 metal features. For the 40nm technology node, optical photolithography utilizes chemically amplified resists to resolve tight via pitches while preserving adequate depth of focus over residual dielectric topography.

During exposure, light absorption activates photoacid generators (PAG) within the resist, releasing acid catalysts. During the subsequent post-exposure bake (PEB), these acid molecules diffuse thermally and cleave polymer protecting groups, rendering the exposed via regions soluble in an alkaline developer solution. Precision control over acid diffusion and exposure energy is necessary to achieve uniform via critical dimensions (CD) across both dense pixel arrays and sparse peripheral logic regions.

Etch Chemistry and Stop-Liner Punch-Through

Following photolithography, the V1 pattern is transferred into the dielectric stack via anisotropic dry plasma etching. The etch sequence consists of a main dielectric etch through the primary ILD 1-2 oxide layer followed by a selective etch through the underlying ILD 1-1 SiCN etch-stop liner. Fluorocarbon-based plasma chemistries are tuned to balance directional ion-assisted chemical etching with sidewall passivation. Polymerizing fluorocarbon species deposit on via sidewalls during etching, preventing lateral undercut and maintaining a vertical via profile across the full dielectric depth.

Etch endpoint control is critical to process yield. The plasma etch must punch cleanly through the SiCN etch-stop liner to expose the M1 metal landing surface without excessively eroding the underlying conductor. Under-etching leaves insulating dielectric residue at the via bottom, creating high contact resistance or electrical opens, while excessive over-etching risks sputtering landing pad metal onto sidewalls or degrading dielectric integrity.

Ashing, Photoresist Strip, and Post-Etch Clean

Once dielectric etching is complete, the remaining photoresist mask, anti-reflective coating, and sidewall fluorocarbon polymers must be thoroughly removed. Oxygen-based plasma ashing oxidizes the organic resist matrix, converting it to volatile gaseous byproducts. Subsequent wet chemical cleaning removes residual inorganic trace contaminants and polymer remnants from the via sidewalls and exposed M1 landing pads without oxidizing the exposed M1 surface. This completes the V1 module, leaving open, pristine via structures ready for subsequent metallization modules.

Interfaces and Failure Propagation

ILD1 Surface to V1 Lithography Interface

Topographical variation on the dielectric surface inherited from underlying M1 metal lines or CMP non-uniformities can cause local resist thickness variations. In thicker resist areas, insufficient optical dose or incomplete PEB deprotection can lead to under-exposed vias, residue at the bottom, or micro-bridging. Conversely, thin resist areas can suffer from over-exposure, producing oversized vias. This CD non-uniformity translates into via resistance variations across the pixel array, degrading sensor signal uniformity.

V1 Etch to Underlying M1 Metal Interface

The interface between the V1 via bottom and the M1 metal landing pad is a major reliability boundary. Excessive over-etching into M1 can sputter metallic species onto via sidewalls, causing dielectric breakdown or lateral leakage paths. Furthermore, incomplete removal of the SiCN etch-stop liner leaves a high-resistance interfacial barrier, degrading signal bandwidth in pixel readout circuits.

Ashing/Clean Integrity and Residue Formation

Incomplete photoresist stripping or inadequate polymer removal leaves a thin fluorocarbon layer at the via bottom or sidewalls. When downstream barrier deposition and metal fill take place, this interfacial polymer contamination leads to poor adhesion, high contact resistance, or catastrophic via peeling under thermal stress.

Optical Reflection in BSI Context

Because light enters from the backside in BSI sensors, front-side interconnect layers act as a rear optical reflector. Non-uniform V1 pattern distribution or density variations across the pixel array can induce spatial variations in optical reflectivity, leading to fixed-pattern noise (FPN) in the final image output.

Walk the Real Module

To trace the step-by-step physical implementation of this module in the process flow, readers can Open V1 Step 164 in the interactive flow.

For an overview of the full sensor manufacturing sequence from substrate preparation to module assembly, refer to the 40nm BSI CMOS Image Sensor process flow article.

Thermal Budget Constraints and Advanced Tradeoffs

Thermal Budget Constraints

Although V1 processing occurs in the BEOL stack, elevated-temperature thermal processing in subsequent modules (such as barrier deposition or metal fill anneals) adds to the cumulative thermal budget. Excess thermal exposure causes lateral diffusion of previously implanted dopants in the pinned photodiode (PPD) and floating diffusion (FD) regions. Broadening of the PPD surface p+ pinning layer or buried n-type storage region degrades full-well capacity and increases dark current generation.

3D Stacking and Backside Thinning Compatibility

In advanced BSI manufacturing, front-side interconnect fabrication is followed by wafer bonding to a host readout wafer and backside substrate thinning. Surface topography or stress non-uniformities originating from V1 patterning and dielectric etching can propagate into downstream layers and cause micro-voids or local stress concentrations during hybrid bonding, leading to silicon defect formation during subsequent backside grinding and chemical etching.

Future Outlook

As CMOS image sensors scale beyond 40nm, 3D logic-stacked BSI architectures separate pixel arrays from readout logic onto distinct wafers joined by direct hybrid bonding. In these architectures, front-side via density over the pixel array can be minimized, reducing optical reflection non-uniformities and crosstalk. At advanced nodes, alternative barrier materials and multi-patterning lithography are replacing single-exposure optical lithography to satisfy tighter via pitch requirements and lower contact resistance.