40nm BSI CMOS Image Sensor First Interlayer Dielectric Integration: Process Flow Principles and Module Logic

Role in the Complete Flow

The 40nm BSI CMOS Image Sensor first interlayer dielectric integration represents a pivotal transition module in the overall fabrication sequence — it bridges the device-level front-end structures (pinned photodiodes, transfer gates, source followers, and silicide contacts) to the first metal interconnect level that will carry signals out of the pixel array [P2]. In a 40nm BSI CMOS Image Sensor process flow, the ILD1 module receives a wafer on which all ion implantation and activation annealing for the photodiode and peripheral transistors have been completed, and where titanium silicide contacts have been formed at the bottom of contact vias using a silicide-last integration scheme [P1]. The module must deliver a planarized, defect-free dielectric stack with properly positioned contact openings and a robust barrier layer, all of which serve as the structural foundation for subsequent metal-one interconnect integration [T1].

The ILD1 module's deliverables are multi-dimensional (Engineering Practice). First, it must provide electrical isolation between adjacent pixel structures and between the pixel array and peripheral circuitry, preventing parasitic leakage paths that would degrade dark current and fixed-pattern noise [P3]. Second, it must serve as a mechanical and chemical barrier that protects the underlying silicide contacts and silicon junctions from contamination during subsequent high-temperature processing steps [P1]. Third, the topmost sub-layer of the ILD1 stack — typically a silicon carbon nitride (SiCN) film — functions as both a diffusion barrier and a selective etch stop that enables precise contact recess alignment when via-one integration is performed in later modules [P1].

From a device physics perspective, the ILD1 stack directly influences the capacitive environment surrounding the floating diffusion node and the source-follower gate [T1]. Any parasitic capacitance introduced by the dielectric stack or by the barrier layer reduces the conversion gain of the pixel, while any fixed charge trapped at dielectric interfaces can shift threshold voltages and increase dark current [P2][P3]. Therefore, the ILD1 module is not merely a passive insulator — it is an active participant in determining the electro-optical performance of the final sensor [P4].

Entry State and Sequence Logic

Upstream Dependencies

When the ILD1 module begins, the wafer has already undergone a carefully ordered sequence of ion implantation and activation annealing steps [T1]. As highlighted in the fabrication of advanced CMOS image sensors, "the orders of ion implantations and activation annealing process steps and their conditions must be carefully tailored to optimize all of the performances simultaneously" [P2]. This means the doping profiles that define the pinned photodiode, the transfer gate channel, and the floating diffusion region are already fixed in the silicon substrate [T1]. The ILD1 module must not disturb these profiles — any excessive thermal budget from dielectric deposition or curing could cause junction diffusion or dopant redistribution that degrades the photodiode's full-well capacity and dark-current characteristics [T1].

In the silicide-last integration scheme used for advanced imagers, titanium silicide (TiSix) contacts are formed by depositing a Ti/TiN barrier stack into pre-etched contact holes and then annealing to form the silicide phase at the silicon interface [P1]. The quality of this silicide formation is highly sensitive to the pre-clean sequence performed immediately before metal deposition [P1]. An optimized flow combining argon plasma with a dry chemical clean (Siconi™) has been shown to "improve yield and reduce drastically the contact chains resistance" in advanced imager technologies [P1]. The ILD1 module receives a wafer where these contacts are already in place, meaning the dielectric deposition must not introduce damage, contamination, or stress that could compromise the contact resistance established by the upstream silicide process [T1].

Downstream Deliverables

The ILD1 module must deliver a surface that is sufficiently planar for the subsequent photoresist patterning and metal etch steps of the M1 interconnect module [A1]. In silicon VLSI technology, intermetal dielectric levels are deposited between global interconnect levels, and "some sort of planarization technique is usually used" to achieve the required topographic uniformity [T1]. For the 40nm BSI CMOS Image Sensor, the planarization challenge is compounded by the dense pixel pitch and the presence of deep contact structures that must be fully filled without voids [P4].

The SiCN barrier sub-layer (ILD 1-1) deposited at the top of the stack must also be tuned to serve as a reliable etch stop for the contact recess step that follows [P1]. This etch-stop function requires the SiCN film to have a sufficiently different etch selectivity relative to the bulk oxide below it, so that when contacts are patterned and etched, the process stops cleanly at the intended depth without punching through into the underlying silicide or silicon junction [P1].

Physical and Chemical Mechanisms

Dielectric Deposition Chemistry

The bulk of the ILD1 stack in a 40nm BSI CMOS Image Sensor consists of silicon dioxide-based films deposited by chemical vapor deposition (CVD) techniques [P4]. As described in silicon VLSI technology, "most intermetal dielectric materials are SiO2 based, often with multilayers utilizing different deposition techniques to obtain SiO2 films with different properties" [T1]. The deposition chemistry involves precursor gases reacting at the wafer surface to form Si–O–Si network structures [T1]. During this reaction, byproducts such as water and hydrogen-containing species are generated and must be driven off through subsequent thermal treatment to prevent voiding and outgassing in later process steps [T1].

The choice of precursor chemistry directly affects film density, step coverage, and gap-fill capability [P4]. Films deposited from silane-based precursors tend to exhibit different conformality and stress characteristics compared to those deposited from organosilane precursors such as tetraethyl orthosilicate (TEOS) [P1]. The former generally provides better gap-fill in narrow structures but may introduce higher compressive stress, while the latter offers improved step coverage on complex topographies but can retain carbon residues that increase film porosity (Engineering Practice).

SiCN Barrier Deposition Integration Principles

The ILD 1-1 SiCN Barrier Deposition integration principles are rooted in the dual requirement for diffusion blocking and etch selectivity [T1]. Silicon carbon nitride is deposited by plasma-enhanced CVD, where silicon, carbon, and nitrogen species are co-deposited to form an amorphous film with a network structure distinct from pure silicon nitride [P1]. The incorporation of carbon atoms modifies the film's dielectric constant, stress state, and etch characteristics relative to conventional silicon nitride [T1].

A key physical principle is that silicon nitride films act as barriers to hydrogen diffusion — as noted in silicon VLSI technology, "a nitride film is a barrier to hydrogen diffusion" [T1]. In the context of the ILD1 stack, this property is critical because hydrogen passivation of silicon dangling bonds at the photodiode surface and at interface states must be performed before the SiCN barrier is deposited [P4]. If the barrier is deposited first, it would block subsequent hydrogen annealing from reaching the underlying interface, leaving unpassivated traps that increase dark current [P4].

The etch-stop function relies on the principle that SiCN exhibits substantially lower etch rates in fluorine-based plasma chemistries compared to silicon dioxide [P1]. When a contact hole is etched through the oxide bulk and reaches the SiCN layer, the etch rate drops sharply, providing a self-limiting mechanism that protects the underlying contact structures [P1]. This selectivity is governed by the relative volatility of etch byproducts: silicon oxide etch products (such as SiF₄) are highly volatile, while silicon nitride and silicon carbide etch products require additional chemical energy to desorb from the surface [P1].

Planarization Mechanisms

After dielectric deposition, chemical mechanical planarization (CMP) is used to flatten the surface topography [T1]. The mechanism involves simultaneous chemical and mechanical action: the polishing slurry chemically softens the oxide surface through hydration and bond breaking, while the mechanical force of the polishing pad removes the softened material [P1]. The removal rate depends on the downforce, relative velocity, and the chemical composition of the slurry (Engineering Practice). For the ILD1 module, achieving global planarization across the pixel array and the peripheral region is essential because any height variation would propagate through subsequent metal levels, compounding alignment and lithographic depth-of-focus challenges [T1].

Interfaces and Failure Propagation

ILD1-to-Silicide Interface

The interface between the bottom of the ILD1 stack and the silicide contacts is one of the most critical boundaries in the entire pixel structure [T1]. If the pre-clean before ILD1 deposition is inadequate, native oxide and organic residues remain at the contact bottom, raising the Schottky barrier height and increasing contact resistance [P1]. Conversely, if the pre-clean is too aggressive — for example, using pure argon plasma bombardment without a complementary chemical clean — it can introduce lattice damage in the silicon substrate that degrades contact reliability and yield [P1].

The failure propagation direction is upward: poor contact quality at the ILD1-to-silicide interface manifests as elevated contact resistance, which in turn reduces the source-follower transconductance, increases readout noise, and can ultimately cause pixel failure [P4]. In contact chain test structures, this appears as a drastic increase in chain resistance, directly impacting yield [P1].

ILD1-to-M1 Interface

The top surface of the ILD1 stack — particularly the SiCN barrier — must provide a clean, well-controlled interface for the subsequent metal-one deposition [P1]. Any contamination, moisture, or particles on this surface will be incorporated into the M1-to-ILD1 boundary, potentially causing adhesion failures or via resistance issues [P4]. The SiCN film's surface chemistry must be compatible with the adhesion layer used for M1 metallization; if the carbon content is too high, it can reduce adhesion and lead to metal delamination during subsequent thermal cycling [P1].

Dielectric-Dielectric Internal Interfaces

Within the ILD1 stack itself, the interface between the bulk oxide and the SiCN barrier is susceptible to charge trapping [T1]. As studied in the context of BSI passivation layers, interface traps (Dit) and fixed charges (Qf) in dielectric stacks can significantly affect device performance [P4]. While that study focused on the backside passivation, the same principles apply to frontside dielectric stacks: "interface trap density originates from broken bonds and structural disorder at the Si/dielectric interface, which introduce energy states within the silicon bandgap and enhance carrier recombination" [P4]. In the ILD1 context, trapped charge at internal dielectric interfaces can shift the threshold voltage of nearby transistors and introduce hysteresis in the pixel's electrical response [T1].

Stress-Induced Failure Propagation

Dielectric films deposited at low temperatures tend to exhibit intrinsic stress — either tensile or compressive depending on the deposition chemistry [T1]. If the ILD1 stack has high tensile stress, it can cause cracking during subsequent thermal cycling, particularly at edges of dense pixel structures where stress concentrates [P4]. Conversely, high compressive stress can cause wafer warpage that degrades lithographic alignment in subsequent levels [P4]. Spin-on-glass (SOG) films, which have been used as gap-fill materials, exhibit "considerable shrinking of the film during these processes, and high tensile stress can result which can cause cracking of the film" [T1]. While SOG is less common in advanced nodes, the stress management principles remain relevant for CVD-deposited films in the 40nm BSI CMOS Image Sensor flow [P4].

Walk the Real Module

The ILD1 module process flow for the 40nm BSI CMOS Image Sensor follows a carefully sequenced series of steps [P2]. The module begins with a wafer entering after silicide contact formation, where the surface contains contact structures with exposed TiSix at the bottom and Ti/TiN barrier layers lining the contact sidewalls [P1].

Step 1: Pre-deposition surface preparation (Engineering Practice). The wafer undergoes a cleaning sequence to remove any organic residues and native oxide regrowth from exposed silicon surfaces [P1]. As established in advanced imager contact processing, a combined approach using physical bombardment followed by a selective dry chemical clean provides the optimal balance between residue removal and substrate damage control [P1]. The physical component removes gross organic contamination, while the chemical component selectively reacts with silicon dioxide through fluorine-based chemistry to form volatile byproducts that are removed under controlled thermal conditions [P1].

Step 2: Bulk ILD1 oxide deposition (Engineering Practice). A silicon dioxide film is deposited by CVD to fill the spaces between contact structures and provide the primary dielectric isolation [P4]. The deposition must achieve conformal coverage and void-free gap fill in the dense pixel regions [P2]. Multiple sub-layers with different deposition chemistries may be stacked to optimize both gap-fill and film density [T1].

Step 3: Planarization (Engineering Practice). Chemical mechanical planarization removes excess dielectric material and produces a flat surface suitable for subsequent lithography [P1]. The CMP step must remove material uniformly across the wafer while minimizing dishing in dense array regions and erosion in isolated areas [P1].

Step 4: ILD 1-1 SiCN barrier deposition [P1]. A thin silicon carbon nitride film is deposited on the planarized oxide surface [P1]. This SiCN deposition serves as the etch stop for subsequent contact recess etching and as a diffusion barrier against moisture and metal contaminants [P1]. The deposition chemistry must be tuned to achieve the required etch selectivity, dielectric constant, and stress characteristics simultaneously [T1].

Step 5: Contact patterning and etching (Engineering Practice). Photoresist is patterned and contact holes are etched through the ILD1 stack [A1]. The etch chemistry transitions through the oxide bulk and stops at the SiCN barrier layer, after which a brief over-etch removes the exposed SiCN to open the contact to the underlying silicide [P1].

To explore the detailed step-by-step interactive flow of this module, you can Open ILD1 Step 161 in the interactive flow, which provides a visual walkthrough of each process step and its integration dependencies (Engineering Practice).

Interfaces and Failure Propagation: Directional Tradeoffs

The Planarization–Gap-Fill Tradeoff

A fundamental directional tradeoff in the ILD1 module exists between achieving aggressive planarization and maintaining void-free gap fill [T1]. Aggressive CMP removal can thin the dielectric in dense pixel regions to the point where the SiCN barrier is partially removed, compromising its etch-stop function [P4]. Conversely, insufficient planarization leaves topographic variations that cause depth-of-focus issues in subsequent lithography (Engineering Practice). The integration engineer must balance the CMP removal amount against the as-deposited dielectric thickness budget, ensuring that the SiCN barrier remains intact across the entire wafer after planarization [T1].

The Selectivity–Damage Tradeoff in Contact Etch

When contacts are etched through the ILD1 stack, the etch process must selectively remove oxide and SiCN while preserving the underlying silicide [P1]. High etch selectivity to the silicide requires lower-energy plasma conditions, but these conditions may leave residual SiCN at the contact bottom, increasing contact resistance [P1]. Conversely, more aggressive etch conditions that ensure complete SiCN removal risk damaging the silicide surface and degrading the Schottky contact quality [P1]. This tradeoff directly echoes the pre-clean challenge described for TiSix contacts, where "conventional Ar plasma pre-clean has limitations in removing native oxide and organic residues, and may introduce damage in n-type silicon, thereby degrading contact resistance and yield" [P1].

The Barrier Integrity–Capacitance Tradeoff

Increasing the SiCN barrier thickness improves its effectiveness as a diffusion barrier and etch stop, but it also increases the parasitic capacitance between the M1 metal and the underlying junctions [P1]. In a 40nm BSI CMOS Image Sensor, this parasitic capacitance directly affects the floating diffusion node capacitance, which in turn determines the conversion gain [P2]. As demonstrated in advanced sensor design, reducing parasitic capacitance at the floating diffusion region is a primary method for improving conversion gain [P2]. Therefore, the SiCN thickness must be minimized while still providing adequate barrier performance — a tradeoff that becomes increasingly tight as the technology node scales [P1].

Related Learning Paths

Engineers studying the 40nm BSI CMOS Image Sensor first interlayer dielectric integration will benefit from exploring adjacent modules in the process flow:

• The overall 40nm BSI CMOS Image Sensor process flow provides the full integration context, showing how the ILD1 module fits between device fabrication and metal interconnect formation [P2].
• The 40nm BSI CMOS Image Sensor metal-one interconnect integration process flow is the direct downstream consumer of the ILD1 module's deliverables — understanding M1 integration clarifies why planarization quality and barrier integrity are so critical [P2].
• The 40nm BSI CMOS Image Sensor via-one integration process flow builds upon the etch-stop functionality provided by the SiCN barrier deposited in ILD1, making it essential reading for understanding the full interconnect stack [P2].

Future Outlook

The ILD1 module for BSI CMOS image sensors is evolving in response to several converging trends [P2]. As pixel pitches continue to shrink and stacking architectures become more prevalent, the ILD1 stack must accommodate tighter pitch requirements while maintaining isolation and barrier performance (Engineering Practice). The emergence of three-dimensional stacked image sensors, where the pixel array wafer is bonded to a separate readout circuit wafer, places additional constraints on the ILD1 module because the dielectric stack must survive wafer bonding thermal budgets without degrading the photodiode characteristics established in the front-end process [P3].

Advanced dielectric materials with lower dielectric constants are being explored to reduce parasitic capacitance at the floating diffusion node, directly improving conversion gain [P2]. However, these materials often have reduced barrier performance and require more complex multi-layer stacks to simultaneously achieve low-k and adequate diffusion blocking [P4]. The integration of high-k dielectric materials, studied extensively for BSI backside passivation [P4], may also find application in frontside dielectric stacks as a means of engineering fixed charge distributions that provide field-effect passivation of interface states.

Finally, the trend toward heterogeneous integration — as exemplified by micro-transfer printing of driver chips onto photodiode layers [A1][A2] — introduces new ILD1 requirements. When driver integrated circuits are printed onto the photodiode layer, the first interlayer dielectric must serve not only as an electrical insulator but also as a mechanical substrate for the printed chips, requiring different stiffness, surface energy, and thermal expansion characteristics than conventional ILD1 stacks [A1].