40nm BSI CMOS Image Sensor First Interlayer Dielectric Integration: Process Flow Principles and Module Logic

Role in the Complete Flow

The 40nm BSI CMOS Image Sensor first interlayer dielectric (ILD1) module represents a critical back-end-of-line (BEOL) dielectric module. Operating immediately after the completion of the first metal layer (M1), ILD1 provides dielectric isolation above M1 while forming the matrix through which via-one contacts are established. Within a complete 40nm BSI CMOS Image Sensor process flow, the ILD1 module receives a wafer that has completed metal-one interconnect integration, establishing the insulation stack required before entering via-one integration.

The primary deliverables of the ILD1 module encompass three key functions:

1. Copper Passivation and Diffusion Control: The initial sub-layer of the ILD1 stack—the ILD 1-1 silicon carbon nitride (SiCN) barrier—functions directly as a copper capping layer and diffusion barrier over the exposed M1 copper patterns. It seals the polished copper surface against oxidation and suppresses copper atom migration into the overlying bulk dielectric under electric fields.
2. Interlevel Electrical Isolation: The bulk dielectric sub-layer (ILD 1-2) fills the inter-metal volume, isolating the M1 wiring pattern from upper interconnect levels and preventing parasitic leakage currents that could degrade pixel dark current and readout noise.
3. Etch Stop and Patterning Matrix: The SiCN capping layer acts as a selective etch stop during subsequent via-one contact recess etching, ensuring that upper via etches do not breach into underlying copper lines or generate micro-voids.

From a device physics perspective, ILD1 thickness and film composition directly alter the capacitive environment around the floating diffusion node and pixel signal routing. Excessive parasitic capacitance on these lines degrades pixel conversion gain and increases RC interconnect delay. Thus, the ILD1 module is a primary determinant of electro-optical conversion efficiency and signal integrity.

Entry State and Sequence Logic

Upstream Dependencies

Prior to ILD1 processing, the wafer undergoes M1 damascene metallization, copper chemical mechanical planarization (CMP), and post-CMP chemical cleaning. At module entry, the wafer surface consists of planarized copper interconnects surrounded by Ta-based barrier liners embedded in the underlying dielectric.

The exposed copper surface at this stage is highly reactive, vulnerable to atmospheric oxidation, and prone to rapid copper diffusion if left unpassivated. However, because backend metallization is already present, the thermal budget for all subsequent ILD1 processes is strictly bounded. All deposition and curing steps must stay within low thermal constraints to prevent thermal stress, copper hillock formation, or degradation of silicide contacts formed in the earlier contact formation module.

Downstream Deliverables

The ILD1 module delivers a multi-layer, passivated dielectric stack with structural and surface integrity ready for via-one photolithography. The deposited SiCN barrier and bulk SiO2 stack must exhibit low stress, defect-free gap fill, and precise uniform thickness across the wafer.

This stable dielectric layer allows downstream modules, particularly via-one integration and second interlayer dielectric integration, to pattern high-aspect-ratio via holes with controlled depth and clean etch stops, ensuring low contact resistance and high yield across the pixel array.

Physical and Chemical Mechanisms

Dielectric Deposition Chemistry and PECVD Principles

Because backend thermal constraints prohibit high-temperature thermal oxidation or atmospheric chemical vapor deposition, the ILD1 stack is fabricated using Plasma-Enhanced Chemical Vapor Deposition (PECVD). By supplying plasma energy to activate reactant gases, the reactions needed for deposition can occur at temperatures much lower than those needed when only thermal energy is provided [T1].

The deposition sequence begins with ILD 1-1 SiCN barrier deposition. In a PECVD chamber, organosilane or silane precursors combined with carbon- and nitrogen-bearing gases undergo plasma dissociation. This forms an amorphous carbon-doped silicon nitride film. Incorporating carbon groups into the silicon-nitrogen lattice lowers the film's polarizability and dielectric constant relative to pure stoichiometric silicon nitride. Simultaneously, ion bombardment from the RF plasma densifies the amorphous network, ensuring a dense physical barrier against copper migration.

Following barrier deposition, ILD 1-2 SiO2 bulk gap-fill deposition is performed. Organosilane precursors such as tetraethyl orthosilicate (TEOS) or silane/oxygen gas mixtures react in the plasma to deposit silicon dioxide. Reaction byproducts, including water vapor and hydrogen species, are evacuated and thermally outgassed to prevent micro-porosity.

Barrier Integrity and Etch-Stop Mechanisms

The SiCN barrier sub-layer relies on dense chemical bonding to block copper diffusion. Copper ions under bias-temperature stress migrate readily through porous oxides; the dense SiCN matrix suppresses copper ion drift and moisture penetration.

Furthermore, fluorine-based plasma chemistries used during subsequent via etching exhibit high selectivity towards silicon dioxide compared to silicon carbon nitride. When a via etch penetrates the bulk oxide, the etch rate decelerates sharply upon reaching the SiCN surface. This provides a self-limiting etch stop that prevents unmanaged deep erosion into the underlying M1 copper lines.

Surface Preparation and Interface Stability

Surface cleanliness before and after dielectric processing is crucial. In chemical mechanical polishing operations associated with backend processing, 3-body contact caused by the pad surface asperities, slurry abrasives nanoparticles and the wafer surface lead to the uniform removal of material from the wafer surface . Post-CMP cleans remove organic residue and copper oxide prior to SiCN deposition, maintaining interface adhesion.

Interfaces and Failure Propagation

M1 Copper-to-SiCN Barrier Interface

The boundary between the polished M1 copper surface and the ILD 1-1 SiCN barrier is the primary path for copper electromigration and dielectric breakdown. If residual native copper oxide or organic cleaning residue remains before SiCN deposition, interfacial adhesion is severely degraded. Under electrical bias and thermal stress, copper atoms migrate along weak interface bonds, leading to void formation, early electromigration failure, and elevated leakage current between adjacent M1 lines.

SiCN-to-Bulk Oxide Interface

The interface between the SiCN capping layer and the overlying ILD 1-2 bulk SiO2 layer is subject to intrinsic stress mismatches. Differences in thermal expansion coefficients and intrinsic film stress (compressive vs. tensile) can cause interface micro-delamination during subsequent thermal cycling. Trapped charges at this dielectric-dielectric interface can also create parasitic electric fields, shifting transistor threshold voltages in nearby pixel readout circuits.

Stress Propagation and Wafer Warpage

PECVD dielectric films inherently accumulate film stress based on RF power, gas pressure, and temperature parameters. High compressive stress across the wafer stack leads to overall wafer warpage, which impairs photolithographic depth-of-focus overlay in subsequent via-one patterning. High tensile stress, on the other hand, can trigger micro-cracking at step edges in dense pixel array boundaries.

Walk the Real Module

The ILD1 module process flow follows a strictly ordered sequence of operational steps:

1. ILD 1-1 SiCN Barrier Deposition. The wafer enters after M1 Cu CMP and post-CMP clean. A thin, dense amorphous carbon-doped silicon nitride film is deposited via PECVD directly on the exposed M1 copper surface. This layer serves as the copper capping layer, diffusion barrier, and subsequent via-one etch stop.
2. ILD 1-2 SiO2 Gap-Fill Deposition. A bulk silicon dioxide film is deposited over the SiCN barrier using PECVD to establish the primary interlevel dielectric thickness and electrical isolation.
3. Pre Litho Cleaning. A post-deposition surface clean and inspection step removes airborne molecules, organic residues, and particles, ensuring surface readiness for via-one photoresist application.

To explore the interactive step sequence in context, you can Open ILD1 Step 161 in the interactive flow.

Directional Tradeoffs

Barrier Density vs. Dielectric Constant (Parasitic Capacitance)

Increasing the density and thickness of the SiCN barrier layer enhances its resistance to copper electromigration and improves the via-one etch-stop process window. However, silicon carbon nitride has a higher dielectric constant than silicon dioxide. Increasing SiCN film thickness or nitrogen density raises the parasitic capacitance between M1 interconnects and nearby floating diffusion nodes, directly decreasing pixel conversion gain. Process engineering requires minimizing SiCN thickness while maintaining sufficient diffusion blocking integrity.

Plasma Density vs. Plasma-Induced Damage

Applying higher RF power and ion bombardment during PECVD densifies the SiCN film and improves copper barrier quality. However, excessive ion bombardment increases compressive stress and risks plasma-induced gate oxide damage or trap generation near active pixel transistors. The plasma regime must balance film compaction against electrical trap generation.

Thermal Budget vs. Film Outgassing

Lower deposition temperatures protect M1 copper lines and lower-level silicide contacts from thermal degradation. However, lower deposition temperatures can lead to incomplete precursor dissociation, leaving unreacted hydrogen or carbon groups in the film that slowly outgas during later thermal steps, causing micro-voids or adhesion degradation.

Related Learning Paths

Engineers studying the ILD1 module should explore adjacent modules in the process flow:

• The master 40nm BSI CMOS Image Sensor Process Flow outlines the complete sequence from front-end pixel creation to back-end stacking.
• The upstream 40nm BSI CMOS Image Sensor Metal-One Interconnect Integration Process Flow covers M1 copper damascene formation and CMP prior to ILD1 deposition.
• The downstream 40nm BSI CMOS Image Sensor Via-One Integration Process Flow details how via-one contact holes are etched down through the ILD1 stack to reach M1.
• The subsequent 40nm BSI CMOS Image Sensor Second Interlayer Dielectric Integration demonstrates how interlevel dielectric concepts extend into higher metallization levels.

Future Outlook

As image sensors scale to smaller pixel pitches and integrate 3D wafer stacking (sensor and logic wafer bonding), the ILD1 module faces evolving integration requirements. Thermal budgets become even tighter, demanding ultra-low-temperature deposition techniques that deliver high film density without thermal degradation.

Advanced low-k capping dielectrics and ultra-thin bilayer barrier stacks are being introduced to minimize RC delay and parasitic capacitance at sensitive floating diffusion nodes. In heterogeneous integration architectures, the ILD1 dielectric stack must also maintain high mechanical rigidity and thermal expansion compatibility to withstand high-stress wafer bonding and backside grinding operations without interface delamination or dark current degradation.