40nm BSI CMOS Image Sensor Metal-One Interconnect Integration: Process Flow Principles and Integration Logic

Role in the Complete Flow

In the 40nm backside-illuminated (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor process flow, the metal-one (MET1) interconnect integration module occupies a pivotal position between the first interlayer dielectric (ILD1) planarization and the upper-level metal stack construction [A2]. The module receives a wafer surface that has already completed all front-end-of-line (FEOL) device fabrication—including pinned photodiode (PPD) formation, transfer gate integration, and floating diffusion (FD) doping engineering—as well as ILD1 deposition and chemical mechanical planarization (CMP) [P2]. At entry, the wafer presents a substantially planarized dielectric surface with metal-zero (MET0) contact structures embedded beneath [T1].

The MET1 module must deliver a patterned metal interconnect layer that provides several critical functions for the 40nm BSI CMOS image sensor [A2]. First, it must establish reliable electrical connections from the MET0 contacts to the pixel source-follower gates, reset transistors, and row-select transistors within each pixel [A2]. Second, it must route signals from the pixel array periphery toward column-level readout circuitry [A2]. Third, because this is a BSI architecture, the frontside metallization—including MET1—can also serve as an optical reflector layer that redirects backscattered photons toward the photodiode, thereby boosting quantum efficiency [P3]. The module must deliver all of this while maintaining extremely low dark current and noise, since any plasma damage or metallic contamination introduced at this stage propagates directly into image quality degradation [P4].

Downstream, the MET1 layer feeds into via-one (VIA1) formation and metal-two (MET2) integration, which together build the multi-level interconnect stack necessary for pixel-to-peripheral signal routing [P1]. The integrity of the MET1 surface topography, line-edge roughness, and dielectric profile directly constrains the lithographic and etch process windows for all subsequent metal layers [T1].

Entry State and Sequence Logic

Upstream Dependencies

The MET1 module in the 40nm BSI CMOS image sensor process flow depends critically on the quality of the ILD1 surface and the underlying MET0 contact architecture [P2]. The 40nm BSI CMOS Image Sensor first interlayer dielectric integration process flow establishes the planarized dielectric matrix into which MET1 trenches will be etched [P1]. Any residual topography from ILD1—whether from incomplete CMP or from density-dependent dishing—translates directly into MET1 trench depth variation, which in turn causes metal line resistance non-uniformity [T1].

Similarly, the 40nm BSI CMOS Image Sensor metal-zero interconnect integration process flow determines the contact resistance and contact landing pad geometry that MET1 must connect to [P1]. If MET0 contacts exhibit lateral offset or insufficient landing area, the MET1 trench must compensate through wider landing pads, which consumes pixel area and reduces fill factor—a parameter that is already under severe pressure in small-pixel BSI sensors [P3].

Module Sequence Rationale

The MET1 module process flow follows a damascene integration sequence (Engineering Practice). The fundamental integration logic is: deposit a dielectric stack (if additional ILD is needed beyond ILD1), pattern the metal trench using photolithography, etch the trench into the dielectric, clean the trench surfaces, deposit a diffusion barrier and metal fill, and then planarize using CMP [P1]. This sequence is chosen because it avoids the metal etch challenges that plagued earlier subtractive aluminum interconnect schemes—particularly the difficulty of etching high-aspect-ratio metal lines at scaled dimensions and the dielectric gap-fill problems that arise between closely spaced metal lines [T1].

In the 40nm BSI CMOS image sensor context, the MET1 TRENCH - Photo integration principles demand special attention because the trench pattern must align not only to MET0 contacts below but also to the pixel grid defined by the photodiode layout [A2]. Any overlay error between the MET1 trench pattern and the underlying pixel architecture can cause signal shorts between adjacent pixels or open circuits between the transfer gate and the FD node [P2].

Physical and Chemical Mechanisms

Lithographic Patterning and KrF Considerations

The METAL 1 TRENCH - Photo step employs krypton fluoride (KrF) lithography in many 40nm BSI CMOS image sensor flows [P2]. The physics of optical lithography dictates that the achievable resolution is governed by the Rayleigh criterion, where the half-pitch is proportional to the exposure wavelength divided by the numerical aperture, scaled by a process-dependent factor [T2]. At the 40nm node, KrF lithography approaches its practical resolution limit for dense metal trench patterns, requiring aggressive resolution enhancement techniques such as optical proximity correction (OPC), phase-shift masks, and off-axis illumination [P1].

The interaction between the photoresist and the underlying dielectric stack is governed by the optics of thin-film interference [P2]. The dielectric stack beneath the resist—typically comprising ILD1 material and possibly a hard mask layer—creates a reflectivity landscape at the resist-dielectric interface [A1]. Standing waves within the resist film cause periodic dose variations that translate into sidewall roughness and critical dimension (CD) variation [T2]. To mitigate this, a bottom anti-reflective coating (BARC) is typically deposited between the dielectric and the resist [A2]. The BARC absorbs incident radiation and destructively interferes with backscattered light, reducing reflectivity to acceptably low levels (Engineering Practice).

Trench Etch Chemistry

After photolithographic patterning, the metal trench is etched into the dielectric (Engineering Practice). The etch chemistry for dielectric materials—typically fluorocarbon-based plasmas—relies on the competition between polymer deposition and ion-enhanced etching [P4]. Fluorine radicals generated in the plasma react with silicon oxide or silicon nitride to form volatile silicon fluoride products, while carbon-containing species deposit fluorocarbon polymer films on sidewalls [T1]. The directional ion flux preferentially clears polymer from the trench bottom, enabling anisotropic etching [T1].

The key physical mechanism is ion-enhanced chemical etching: neutral fluorine radicals provide the chemical reactivity, while energetic ions accelerated through the plasma sheath provide directional energy that both enhances the chemical reaction at the trench bottom and suppresses lateral etching [P4]. The balance between polymer accumulation and ion-driven removal determines the trench sidewall angle, trench depth uniformity, and CD bias relative to the photoresist pattern [P1].

For the 40nm BSI CMOS image sensor, an additional consideration is the selectivity of the dielectric etch to any exposed silicon or silicide surfaces at the MET0 contact openings [P2]. If the etch reaches the MET0 contacts, over-etch into the underlying contact metal can increase contact resistance or even sever the contact entirely [T1].

Barrier Deposition and Metal Fill

Following trench etch and post-etch cleaning, a diffusion barrier—typically a refractory metal nitride such as titanium nitride (TiN) or tantalum nitride (TaN)—is deposited by physical vapor deposition (PVD) or atomic layer deposition (ALD) [T1]. The barrier serves two functions: it prevents metal atoms from diffusing into the surrounding dielectric or into the silicon substrate, and it provides adhesion between the metal fill and the dielectric sidewalls [A1].

The physics of barrier deposition involves conformal coating of high-aspect-ratio trench geometries [P2]. PVD processes suffer from non-conformal step coverage due to the directional nature of sputtered atom flux, leading to thinning at trench sidewalls and thickening at trench corners [P2]. ALD, by contrast, provides highly conformal coverage through self-limiting surface reactions, but at the cost of lower throughput (Engineering Practice). In the 40nm BSI CMOS image sensor, the barrier must be thin enough to leave adequate cross-sectional area for the metal conductor, yet thick enough to prevent diffusion—a fundamental tradeoff [A2].

The metal fill is then deposited by electroplating for copper metallization or by PVD/CVD for aluminum or tungsten metallization [P1]. For copper damascene integration, a copper seed layer is first deposited by PVD to provide a conductive path for electroplating [P2]. The seed layer must be continuous and sufficiently thick to initiate plating, particularly at the bottom of narrow trenches where seed discontinuity causes void defects [T1].

Chemical Mechanical Planarization

The final step in the MET1 module is CMP, which removes the excess metal and barrier material from above the dielectric surface, leaving metal only within the trenches [P1]. The CMP mechanism involves simultaneous chemical and mechanical action: the slurry chemically oxidizes or complexes the metal surface, and the mechanical abrasion from slurry particles removes the weakened surface layer (Engineering Practice). The polishing speed depends on the applied pressure, relative velocity between the pad and wafer, and the chemical activity of the slurry [T1].

In the 40nm BSI CMOS image sensor, CMP uniformity is critical because the pixel array region typically has a very different metal pattern density than the peripheral circuit region [A2]. Dense metal patterns in the periphery polish differently than sparse patterns in the pixel array, leading to metal dishing in wide trenches and dielectric erosion in dense regions [A1]. These topography variations propagate upward through subsequent metal layers and can cause lithographic focus errors at higher levels [P1].

Interfaces and Failure Propagation

MET0-to-MET1 Interface

The interface between MET0 contacts and MET1 trenches is a primary site for failure propagation (Engineering Practice). If the MET1 trench etch does not fully clear the dielectric over the MET0 contact landing pad, the resulting high-resistance connection degrades signal transfer from the photodiode to the readout circuitry [P2]. Conversely, if the etch over-clears, it can undercut the MET0 contact and create voids that trap process residues, leading to long-term reliability failures (Engineering Practice).

Metallic contamination at this interface is particularly dangerous for CMOS image sensors [P4]. Transition metals such as iron, copper, or tungsten that diffuse from the interconnect into the silicon substrate create deep energy levels within the bandgap, acting as generation-recombination centers [T1]. These centers increase dark current, produce white spot defects, and degrade the recombination lifetime that governs charge transfer efficiency in the PPD [P4]. The proximity gettering approach described in [P4]—using hydrocarbon molecular ion implantation to create buried gettering sinks—can mitigate this risk by capturing diffusing metal impurities before they reach the device active region.

MET1-to-VIA1 Interface

The MET1 surface condition after CMP directly governs the quality of the VIA1 connection [P1]. Residual oxide or copper oxide on the MET1 surface creates a barrier layer at the VIA1 interface, increasing via resistance and potentially causing open-circuit failures [P1]. Copper dishing—the recession of the copper surface below the dielectric plane in wide trenches—creates a topographic step that the VIA1 lithography must accommodate [P1]. If dishing is severe, the via photoresist may not resolve at the bottom of the recessed region, leading to missing vias [P1].

Dielectric Integrity

The dielectric material surrounding MET1 trenches must maintain its insulating properties throughout subsequent thermal processing [P1]. In the 40nm BSI CMOS image sensor, low-k dielectric materials may be employed to reduce inter-line capacitance, which directly affects RC delay and signal crosstalk between adjacent pixel readout paths [P1]. However, low-k materials—particularly porous carbon-doped oxides—are mechanically weaker and more susceptible to plasma damage than dense silicon oxide [P1].

Plasma damage during MET1 trench etch can break Si-C bonds in carbon-doped oxide, creating silanol groups that absorb moisture and increase the effective dielectric constant, negating the capacitance benefit [P4]. Furthermore, the reduced mechanical modulus of low-k materials makes them vulnerable to delamination during packaging or thermal cycling, which can cause catastrophic interconnect opens [P1].

Optical Interface Considerations

In BSI CMOS image sensors, the MET1 layer is on the frontside of the wafer—the side opposite the light-illuminated backside [A2]. However, MET1 still plays an optical role: it can serve as a reflector that redirects photons that pass through the photodiode back toward the photosensitive region, effectively increasing the optical path length and improving QE, particularly for near-infrared wavelengths where silicon absorption is weak [P3]. The reflectivity of MET1 depends on the metal used, its surface roughness after CMP, and any dielectric capping layers [P1]. A rough or oxidized MET1 surface scatters light rather than reflecting it specularly, reducing the reflectivity benefit [P2].

Walk the Real Module

The interactive process flow for the 40nm BSI CMOS image sensor MET1 module provides a step-by-step view of how each process step sequences into the complete integration [P2]. You can explore the detailed module steps starting from Open MET1 Step 151 in the interactive flow, which illustrates the real sequence of deposition, lithography, etch, clean, barrier deposition, metal fill, and CMP operations that constitute the MET1 integration [P1].

For a broader understanding of how MET1 fits into the complete 40nm BSI CMOS Image Sensor process flow, the full process architecture from FEOL through backside thinning and color filter assembly provides the context in which each MET1 design decision is evaluated [P2].

Related Learning Paths

Engineers studying the MET1 module should also explore the immediately adjacent modules in the 40nm BSI CMOS image sensor flow:

• ILD1 Integration: Understanding the dielectric stack that MET1 trenches are etched into is essential, as dielectric material properties and planarization quality directly constrain MET1 patterning and CMP windows [P1]. The 40nm BSI CMOS Image Sensor first interlayer dielectric integration process flow article covers these upstream dependencies [P2].

• MET0 Interconnect Integration: The contact-level interconnect that MET1 connects to sets the landing pad geometry, contact resistance, and overlay budget that MET1 must accommodate [P1]. The 40nm BSI CMOS Image Sensor metal-zero interconnect integration process flow article explores these foundational constraints [P1].

• BSI Process Flow Overview: The complete process architecture, including how frontside metallization interacts with backside thinning, color filter array deposition, and microlens formation, is covered in the 40nm BSI CMOS Image Sensor process flow article [P2]. This broader context is critical for understanding why MET1 optical reflectivity and metal contamination control matter for final image sensor performance [P2].

Future Outlook

The evolution of 40nm BSI CMOS image sensor technology points toward several emerging trends in MET1 integration [P2]. First, three-dimensional (3D) stacking of pixel array and logic chips—using through-silicon vias (TSVs) and hybrid bonding—is reshaping the role of MET1 [A1]. In stacked architectures, the pixel chip's MET1 no longer needs to carry long-distance routing signals, since the logic chip handles complex signal processing [A1]. This relaxation allows MET1 to be optimized purely for pixel-level connectivity and optical reflectivity [A1][A2].

Second, the drive toward smaller pixels—at increasingly scaled pitches in consumer mobile applications—places increasing pressure on MET1 lithographic resolution [P1]. While KrF lithography has served the 40nm node well, future pixel scaling may require immersion ArF lithography or even EUV for metal trench patterning, with associated changes in photoresist chemistry, BARC design, and etch selectivity requirements [P1].

Third, advanced gettering strategies—including proximity gettering via hydrocarbon molecular ion implantation—are becoming essential as thermal budgets shrink and conventional intrinsic gettering becomes ineffective [P4]. These techniques directly benefit MET1 integration by reducing the risk of metal contamination from interconnect processing [P4].

Finally, the co-optimization of MET1 as both an electrical interconnect and an optical reflector represents a unique opportunity specific to BSI image sensors [A2]. Engineering the MET1 surface morphology and capping layer stack to maximize reflectivity at targeted wavelengths—while maintaining electrical performance and reliability—will continue to be an active area of process integration research [P3].