40nm BSI CMOS Image Sensor Metal-Zero Interconnect Integration: Process Flow, Mechanisms, and Integration Logic

Role in the Complete Flow

In the 40nm back-side illuminated (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor fabrication sequence, the metal-zero (MET0) interconnect module occupies a pivotal position: it is the first metallization layer that bridges device-level contact structures to the upper routing network. Upstream, MET0 receives a wafer where front-end-of-line (FEOL) device formation—including photodiodes, transfer gates, and peripheral transistors—has been completed, and where contact holes have been filled and planarized through chemical mechanical polishing (CMP). A high resistivity dielectric layer, usually silicon dioxide, separates the active regions from the first level global interconnect, and electrical contact is made between the interconnect and the active regions in the silicon through openings in that dielectric layer [T1]. The contact plugs, typically tungsten (W), provide vertical electrical pathways from the silicided source/drain regions to the MET0 landing pads.

Downstream, MET0 must deliver a low-defect, low-resistance interconnect pattern that subsequent metal levels—such as the 40nm BSI CMOS Image Sensor metal-one interconnect integration process flow—can reliably build upon. In a BSI architecture, illuminating the photodiode array from the backside avoids optical blockage by the front-side metallization stack, requiring substrate thinning so light can reach the active depletion region [T2]. This means that any contamination, particle, or pattern defect introduced at MET0 will be permanently embedded beneath the photodiode layer after the BSI conversion, making defect prevention at this stage extraordinarily consequential.

Post-CMP cleaning of wafers serves as a key step in successful chemical mechanical polishing integration sequences [P2]. At the entry of the MET0 module, cleaning the polished contact surface removes residual slurry particles, metallic ions, and organic residues before blanket metal deposition. In advanced image sensors, where dark current and white pixel defects are extremely sensitive to trace metallic contamination, the cleanliness of the interface beneath MET0 directly influences final image quality.

Entry State and Sequence Logic

Upstream Dependencies

The MET0 module begins immediately after the contact module has polished the tungsten plugs flush with the surrounding inter-level dielectric (ILD). The 40nm BSI CMOS Image Sensor contact formation process flow delivers a planar surface where contact plugs land on silicided silicon active areas—often titanium silicide or nickel silicide. The quality of this contact interface depends on pre-cleans and barrier integrity before W plug deposition.

Before MET0 film deposition and patterning can begin, the incoming wafer must satisfy several strict integration conditions:

• The post-CMP contact surface must be thoroughly cleaned of slurry nanoparticles and chemical residues to prevent interfacial high resistance or peeling of the MET0 metal stack.
• Contact plug tops must be free of heavy oxidation or organic stains to ensure low contact resistance between the W plug and MET0 W layer.
• Residual metallic contamination from upstream processing must be contained, as ungettered mobile impurities can diffuse into the photodiode active region, introducing deep energy levels within the silicon bandgap and inducing Shockley-Read-Hall generation-recombination centers.

Sequence Ordering Rationale

Unlike upper dual-damascene copper interconnect levels, MET0 in this 40nm BSI CIS architecture uses a subtractive metallization scheme: blanket tungsten deposition over an adhesion/barrier liner, photolithographic patterning, plasma dry etching, and resist stripping/cleaning. Within the broader 40nm BSI CMOS Image Sensor process flow, completing MET0 as a subtractive tungsten layer offers critical thermal and mechanical advantages. Tungsten provides exceptional thermal stability during downstream dielectric depositions and resists stress migration under front-to-back thermal cycles.

Physical and Chemical Mechanisms

Contact Surface Post-CMP Clean Mechanics

The initial post-CMP clean at step 125 removes three main contaminant types from the contact surface: slurry abrasive particles (typically silica or alumina), metallic ions from polishing chemicals and pad wear, and organic residue films. Chemical dissolution converts surface metallic remnants into soluble chelate complexes, while physical forces—such as megasonic cavitation or PVA brush scrubbing—overcome electrostatic and van der Waals adhesion to dislodge sub-micron particles without scratching the dielectric.

Selective chemistry is essential during this stage. The cleaning solution must remove slurry particulates and trace metals while preserving the underlying ILD surface roughness and preventing galvanic corrosion or recess of the exposed W contact plugs.

Subtractive Tungsten Deposition and Film Adhesion

Following post-CMP cleaning, a thin adhesion and diffusion barrier liner (such as Ti/TiN or TiN) is deposited, followed by chemical vapor deposition (CVD) of blanket tungsten. The liner serves a dual purpose: it prevents reaction between tungsten fluorides (used during CVD) and the underlying dielectric, while promoting strong mechanical adhesion to both the ILD oxide and the exposed W plug surfaces. CVD W deposition relies on the reduction of tungsten hexafluoride (WF6) using hydrogen (H2) or silane (SiH4) precursor chemistry, yielding a dense, low-stress metallic film across the wafer.

Subtractive Plasma Etching and Anisotropic Profile Control

After pre-litho cleaning and photolithographic exposure of the MET0 pattern, reactive ion etching (RIE) subtractively transfers the photoresist pattern into the tungsten and barrier stack. Fluorine- or chlorine-based plasma chemistries (such as SF6/Cl2/N2) react with tungsten to form volatile halides (WF6, WCl6) that are pumped away from the reaction chamber. Passivating sidewall species maintain anisotropic vertical profiles, preventing isotropic undercut of narrow MET0 lines.

The plasma etch must exhibit high selectivity to the underlying ILD dielectric. Uncontrolled over-etching into the dielectric can form severe micro-trenches along the line edges, creating topography traps that degrade planarization during subsequent dielectric deposition following MET0.

Photoresist Ashing and Post-Etch Residue Removal Chemistry

Once W plasma etching defines the MET0 interconnect lines, the remaining photoresist mask and halogenated plasma polymer residues must be stripped. Oxygen-based plasma ashing oxidizes the organic resist into volatile CO2 and H2O. Subsequent wet chemical cleaning dissolves inorganic metal-halide sidewall polymers without corroding the fine tungsten metal lines or etching the underlying contact ILD.

Interfaces and Failure Propagation

MET0-to-Contact Interface

The interface between the MET0 landing pad and the underlying contact plug represents a primary electrical failure node. If organic residues or oxide films remain on top of the W contact plug after step 125 cleaning, interfacial contact resistance increases sharply. In image sensor readout circuits, elevated contact resistance increases thermal noise and RC delay, degrading pixel signal-to-noise ratio (SNR) and frame readout speed.

MET0-to-ILD Interface & Adhesion

Subtractive MET0 lines sit directly on the planarized contact ILD surface. Poor clean quality or inadequate barrier liner adhesion can cause line peeling or micro-delamination during subsequent thermal processing. Furthermore, if plasma over-etching roughens the ILD surface adjacent to MET0 lines, local electric field concentration can increase dielectric leakage current between neighboring interconnect tracks.

Contamination Propagation into Pixel Region

In BSI CMOS image sensors, front-side metallization layers are fabricated prior to wafer bonding and backside substrate thinning. During backside mechanical grinding and chemical etching, bulk silicon gettering sites (such as oxygen precipitates) are physically removed. Consequently, any trace metallic contaminants (such as Cu, Fe, or Ni) left uncleaned at the MET0 level can thermally diffuse into the photodiode active region during subsequent thermal steps. These deep-level impurities introduce energy states in the bandgap that increase dark current and white pixel defect counts across the pixel array.

Line Topography and Downstream Lithography

Because MET0 is formed by subtractive etching, it leaves relief topography that subsequent dielectric deposition must accommodate. In this flow, additional PMD deposition and another contact-opening and metallization sequence intervene before M1 patterning. The named ILD1 module occurs after M1, so it must not be inserted between MET0 and M1 or described as a listed CMP operation immediately following MET0. Dielectric coverage and interface quality remain important because seams, voids or residue can compromise later insulation and connections.

Walk the Real Module

To inspect the exact step sequence of the MET0 module in the 40nm BSI CMOS image sensor fabrication flow, readers can Open MET0 Step 125 in the interactive flow. This interactive flow illustrates how post-CMP cleaning transitions into tungsten deposition, lithography, dry etching, and post-etch residue removal.

The subtractive MET0 module follows a cohesive integration logic: contact CMP surface preparation (step 125) ensures low contact resistance; blanket tungsten deposition (step 126) builds the conductor layer; pre-litho cleaning (step 127) and photolithography (step 128) define line features; reactive plasma etching (step 129) isolates the metal tracks; and photoresist ashing/cleaning (step 130) prepares the surface for the subsequent PMD dielectric deposition and contact-module processing.

BSI-Specific Integration Considerations

Backside Deep Trench Isolation Alignment

In BSI image sensors, backside deep trench isolation (BDTI) trenches are etched from the thinned silicon back surface to isolate individual pixel photodiodes. BDTI structures must align accurately with front-side shallow trench isolation (STI) patterns. Local stress or wafer warping induced by dense MET0 tungsten metal patterns can introduce distortion during wafer bonding and thinning, indirectly degrading BDTI lithographic overlay precision.

Thermal Budget Compatibility

The thermal budget of the MET0 module—including CVD W deposition temperatures and post-etch clean bakes—must be bounded to protect the underlying silicided contact structures and FEOL dopant profiles. Excessive thermal exposure can trigger phase transformation or agglomeration in silicided contacts, dramatically increasing contact resistance. Bounding the MET0 thermal budget preserves pixel pinning layer dopants and prevents dark current degradation.

Related Learning Paths

Engineers exploring BSI CMOS image sensor manufacturing can build a comprehensive understanding through these connected topics:

• The overall 40nm BSI CMOS Image Sensor process flow provides module-level context for the complete image sensor process.
• The 40nm BSI CMOS Image Sensor contact formation process flow details the contact CMP and silicide steps directly preceding MET0.
• The 40nm BSI CMOS Image Sensor metal-one interconnect integration process flow covers the immediate downstream copper damascene interconnect module.

Future Outlook

As image sensor pixel pitches scale down, MET0 integration faces heightened challenges in line pitch scaling, parasitic capacitance reduction, and defect control. Advanced cleaning chemistries and dry plasma cleaning processes are being introduced to minimize interfacial residues without etching delicate dielectric surfaces. Simultaneously, improved plasma etch monitoring techniques help control profile angles and minimize dielectric recess, ensuring robust gap-fill and high yield for advanced BSI CIS devices.