40nm BSI CMOS Image Sensor Contact Formation: Process Flow, Mechanisms, and Integration Logic

Role in the Complete Flow

In the 40nm Backside Illumination (BSI) CMOS Image Sensor process flow, the contact formation module serves as the critical bridge between front-end-of-line (FEOL) device fabrication and back-end-of-line (BEOL) metallization. By the time this module begins, the photodiode arrays, transfer gates, floating diffusion nodes, and peripheral source/drain regions have all been fabricated, silicided where required, and encapsulated beneath a pre-metal dielectric (PMD) stack. The contact module must open vertical vias through that dielectric to expose the underlying silicon or silicide surfaces, then fill those vias with barrier and metal layers to establish low-resistance electrical pathways.

What this module receives from upstream is a planarized dielectric landscape with varying thicknesses over gate electrodes, active source/drain regions, and local interconnects. The topography is partially smoothed by chemical mechanical planarization (CMP), but residual step-height differences remain across the pixel array and peripheral logic regions. What the contact module must deliver downstream is a set of electrically reliable, vertically isolated conductive pathways that connect the Metal 0 interconnect level to the underlying device terminals. These pathways must exhibit low contact resistance, high yield, and long-term reliability under thermal and electrical stress.

For a CMOS image sensor specifically, the contact module carries additional constraints. The pixel region demands minimal metallic coverage near the photodiode to preserve optical sensitivity and reduce dark current, which influences the silicide-last integration strategy and contact placement rules. The peripheral logic region, by contrast, requires dense contact arrays to support high-speed signal processing. The contact module must therefore satisfy two divergent sets of requirements simultaneously within a single wafer.

The downstream consumer of this module's output is the 40nm BSI CMOS Image Sensor metal-zero interconnect integration process flow, where Metal 0 lines and vias are patterned atop the contact plugs. Any defect, void, or resistive interface introduced during contact formation propagates directly into Metal 0 continuity and pixel readout fidelity.

Entry State and Sequence Logic

Upstream Dependencies

The contact module enters after the PMD deposition and planarization sequence has been completed. The 40nm BSI CMOS Image Sensor pre-metal dielectric integration process flow delivers a dielectric stack whose composition and topography directly influence contact etch depth uniformity. Because the PMD thickness varies over active regions versus gate stacks, the contact etch must contend with non-uniform dielectric depths, requiring highly selective etch chemistries to avoid over-etching shallow regions while under-etching deep ones.

The silicide strategy chosen upstream also constrains the contact module. In the 40nm BSI CMOS Image Sensor, a silicide-last integration is commonly adopted in pixel regions, meaning titanium silicide (TiSiₓ) is formed during the contact module itself by depositing and annealing a titanium/titanium nitride (Ti/TiN) barrier stack. This differs from standard logic flows where silicidation is completed in the FEOL. The silicide-last approach minimizes metal proximity to photodiodes but introduces additional surface preparation challenges during contact formation.

Detailed Step-by-Step Topology Sequence

The contact formation module follows a strict multi-stage sequence to open, clean, and metallize the contact vias:

1. Metal 0 Gate and S/D Contact Opening - Photo (Step 112): Photolithography defines the contact hole pattern using resolution enhancement techniques to establish critical dimensions.
2. PMD 3 Etch (Step 113): Anisotropic plasma etching removes the upper oxide layer of the PMD stack.
3. PMD 2 Etch (Step 114): Plasma etching continues through the middle dielectric layer, maintaining anisotropic sidewall profiles.
4. PMD 1 Etch (Step 115): The primary dielectric etch penetrates the lower PMD layer, approaching the contact etch-stop layer (CESL).
5. CESL 2 Etch (Step 116): Highly selective plasma etching breaks through the upper silicon nitride etch-stop layer.
6. CESL 1 Etch (Step 117): Etching penetrates the lower etch-stop film, exposing the underlying pad oxide.
7. Pad Oxide Etch (Step 118): A controlled oxide etch exposes the silicon or silicide surface at the contact base.
8. Poly/Si Back Etch (Step 119): A light surface etch cleans residual recessed silicon or polysilicon interfaces.
9. Ashing & Strip/Clean (Step 120): Photoresist is ashed in an oxygen plasma, followed by wet chemical cleaning to strip organic residues and fluorocarbon polymers.
10. Ti/TiN Deposition (Step 121): Conformal physical vapor deposition (PVD) or chemical vapor deposition (CVD) deposits the titanium adhesion layer and titanium nitride barrier film.
11. W Deposition (Step 122): Chemical vapor deposition fills the contact via with bulk tungsten.
12. W CMP (Step 123): Chemical mechanical planarization removes overburden tungsten, stopping on the barrier layer.
13. TiN/Ti CMP (Step 124): Secondary CMP removes overburden barrier metal, isolating individual tungsten contact plugs in the dielectric field.

Physical and Chemical Mechanisms

Lithographic Patterning and Resist Flow

The contact hole lithography step at the 40nm node faces fundamental optical diffraction limits. Krypton fluoride (KrF) lithography produces aerial images whose contrast diminishes for features approaching the resolution boundary. To extend the practical resolution without introducing cost-prohibitive exposure equipment, a resist flow process (RFP) can be employed. After exposure and development, a thermal treatment drives the photoresist polymer above its glass transition temperature, causing viscoelastic flow that shrinks the contact hole inward.

The physics underlying RFP rests on polymer chain mobility. Below the glass transition temperature, polymer segments are locked in a glassy state with negligible flow. Above it, segments acquire thermal energy to undergo cooperative motion, and the resist profile relaxes under surface tension. Crosslinkable functional groups within the resist simultaneously undergo thermally activated crosslinking, which stabilizes the polymer network and prevents excessive deformation. The interplay between flow kinetics and crosslinking kinetics determines the final critical dimension (CD) and profile shape.

Multi-Stage Dielectric and Liner Etch Dynamics

After patterning, the contact holes are transferred into the PMD stack by anisotropic plasma etching across multiple stages (PMD 3, PMD 2, and PMD 1 Etch). Fluorocarbon-based chemistries are used, where polymerizing etch gases deposit fluorocarbon polymer on sidewalls to provide profile control while ion bombardment drives vertical etching at the hole bottom.

When the etch approaches the underlying substrate, it transitions to the Contact Etch Stop Layer (CESL 2 and CESL 1 Etch) and Pad Oxide Etch stages. Silicon nitride CESL layers provide high etch selectivity relative to oxide, allowing the plasma etch to pause across varying PMD thicknesses without punching through shallow junctions. Finally, a controlled wet or dry oxide etch clears the pad oxide, and a Poly/Si Back Etch cleans the exposed silicon surface. Selectivity is achieved through chemical reaction kinetics rather than automatic physical stops, requiring careful timing to avoid substrate pitting.

Pre-Clean, Substrate Damage Control, and Surface Preparation

Following photoresist ashing and polymer stripping (Step 120), the exposed silicon at the contact bottom must be prepared for metallization. Conventional argon (Ar) plasma sputter etching can physically remove native oxide, but ion bombardment introduces lattice damage in n-type silicon, increasing contact resistance. Dry chemical cleans (such as Siconi™) offer a gentler alternative: remote plasma generates ammonium fluoride (NH₄F) species that react selectively with SiO₂ to form volatile ammonium fluorosilicate salts, which are subsequently sublimated with mild heating.

A dual pre-clean sequence combines physical and chemical mechanisms. Ar plasma removes organic residues, while the subsequent dry chemical clean removes native oxide without lattice damage. Because fluorine-containing reactions attack SiO₂ preferentially over silicon, the single-crystal silicon lattice remains intact, maintaining low contact resistance.

Schottky Barrier Physics and Contact Resistance

The fundamental physics of metal-silicon contact resistance is governed by the Schottky barrier height at the interface. When a metal contacts silicon, the difference in work functions creates a potential barrier that impedes carrier flow. For heavily doped silicon, quantum mechanical tunneling through the thin barrier dominates, and contact resistance decreases exponentially with increasing doping concentration. In standard contact plug integration, a tungsten plug process is applied over titanium nitride barrier and titanium adhesion layers [P2]. Titanium nitride films are widely used as a diffusion barrier for tungsten contact plugs and copper interconnections [P5].

In the 40nm BSI CMOS Image Sensor, contact resistance is particularly critical because pixel readout circuits operate at low signal levels. Any excess series resistance at the source follower or transfer gate contact degrades conversion gain and increases readout noise. Depositing titanium directly onto cleaned silicon creates a low-barrier TiSiₓ interface upon annealing, significantly lowering contact resistance compared to un-silicided contacts.

Interfaces and Failure Propagation

Lithography-to-Etch Transfer

The contact hole CD defined by lithography directly determines the post-etch via dimension. If the resist flow process over-shrinks the hole, the resulting narrow via restricts metal deposition and increases resistance. If it under-shrinks, adjacent contacts may merge after etch, creating electrical shorts. A re-entrant or bowed resist profile transfers into the dielectric as an irregular via shape, leading to keyhole voiding during tungsten deposition.

Etch-to-Clean and Interfacial Contamination

After dielectric etch, residual fluorocarbon polymers coat the sidewalls and bottom of contact holes. If these residues are not fully removed during Ashing & Strip/Clean (Step 120), they act as insulating barriers between the barrier metal and the underlying silicon. Insufficient cleaning leads to high contact resistance or non-linear Schottky behavior.

Conversely, aggressive pre-cleaning can cause CD enlargement or salt accumulation. Sublimation of ammonium fluorosilicate salts must be fully completed; un-sublimated salt residues leave fluorinated interfacial contamination that blocks silicide reaction during subsequent thermal steps.

Clean-to-Barrier/Metallization Interface

The pre-clean leaves the silicon surface chemically active and highly susceptible to native oxide regrowth. The queue time between cleaning and Ti/TiN Deposition (Step 121) must be strictly controlled. Residual interfacial oxide prevents titanium from reacting uniformly with silicon, producing non-uniform TiSiₓ films and high contact resistance variance.

During CVD tungsten deposition (Step 122), tungsten hexafluoride (WF₆) precursor reacts with the underlying barrier. If the TiN barrier film has pinholes or inadequate sidewall coverage, fluorine species can penetrate the barrier and react with underlying titanium or silicon, causing "volcano" expansion defects and junction leakage.

Downstream Failure Propagation and Process Monitoring

Failures in the contact module propagate into multiple downstream effects. High contact resistance increases the source follower resistance in pixel circuits, reducing the signal-to-noise ratio and degrading image quality. Unfilled contact vias or tungsten keyhole voids suffer from electromigration failure under sustained current stress.

As a process monitor, contact resistance is also measured in long contact chains [T1]. These test structures, consisting of hundreds or thousands of contacts connected in series across varying topographies, allow inline electrical testing to detect contact opening failures, high interfacial resistance, and lot-to-lot process shifts.

Walk the Real Module

To explore the step-by-step sequence of the 40nm BSI CMOS Image Sensor contact formation process flow, you can Open CONTACT Step 112 in the interactive flow. This interactive module walks through each process step in order, showing the entry conditions, processing actions, and exit deliverables that define the contact formation sequence.

The interactive flow illustrates how the Metal 0 Gate and S/D Contact Opening - Photo step fits within the broader CONTACT module process flow, preceded by PMD planarization and followed by multi-stage dielectric etches, cleaning, and metallization steps. By stepping through the sequence, you can observe the integration logic that governs how each step's output constrains the next step's process window.

For the broader context of where contact formation sits within the complete 40nm BSI CMOS Image Sensor process flow, refer to the 40nm BSI CMOS Image Sensor process flow overview, which maps the full module sequence from device isolation through final metallization.

Related Learning Paths

Engineers studying contact formation should explore several adjacent modules to build a complete integration picture:

• The pre-metal dielectric module directly feeds the contact etch and determines the dielectric landscape through which contacts must be etched. Understanding PMD material selection, deposition conformality, and planarization strategy is essential for predicting contact etch uniformity. Refer to the PMD integration process flow article for this context.

• The Metal 0 interconnect module consumes the contact module's output. The contact plug tops must be planarized and exposed sufficiently for Metal 0 landing pad patterning. The Metal 0 interconnect integration article covers the downstream requirements.

• For engineers interested in device physics, metal-semiconductor junction theory provides the theoretical grounding for understanding why contact resistance scales with doping, barrier height, and interfacial cleanliness.

Future Outlook

The 40nm BSI CMOS Image Sensor contact formation process reflects a mature, highly optimized integration scheme. As pixel pitch continues to scale in advanced image sensors, contact formation faces increasing aspect ratios, tighter overlay margins, and more stringent contact resistance requirements. The trend toward 3D wafer stacking—where pixel arrays and logic circuits are fabricated on separate wafers and joined via hybrid bonding—is shifting high-density interconnect requirements to direct copper-to-copper interfaces, redefining traditional contact module architectures.