40nm BSI CMOS Image Sensor Contact Formation: Process Flow, Mechanisms, and Integration Logic

Role in the Complete Flow

In the 40nm BSI CMOS Image Sensor process flow, the contact formation module serves as the critical bridge between front-end-of-line (FEOL) device fabrication and back-end-of-line (BEOL) metallization [P3]. By the time this module begins, the photodiode arrays, transfer gates, floating diffusion nodes, and source/drain regions have all been formed, silicided where required, and encapsulated beneath a pre-metal dielectric (PMD) stack [P2]. The contact module must open vertical vias through that dielectric to expose the underlying silicon or silicide surfaces, then fill those vias with barrier and metal layers to establish low-resistance electrical pathways [T1].

What this module receives from upstream is a planarized dielectric landscape with varying thicknesses over gates, source/drain regions, and local interconnects [A1]. The topography is partially smoothed by chemical mechanical planarization (CMP), but residual step-height differences remain across the pixel and peripheral circuitry areas [T1]. What the contact module must deliver downstream is a set of electrically reliable, vertically isolated conductive pathways that connect the Metal 0 interconnect level to the underlying device terminals [T2]. These pathways must exhibit low contact resistance, high yield, and long-term reliability under thermal and electrical stress [P1].

For a CMOS image sensor specifically, the contact module carries additional constraints [P2]. The pixel region demands minimal metallic coverage near the photodiode to preserve optical sensitivity, which influences the silicide-last integration strategy and contact placement rules [P1]. The peripheral logic region, by contrast, requires dense contact arrays similar to standard logic flows (Engineering Practice). The contact module must therefore satisfy two divergent sets of requirements simultaneously within a single wafer [A1].

The downstream consumer of this module's output is the 40nm BSI CMOS Image Sensor metal-zero interconnect integration process flow, where Metal 0 lines and vias are patterned atop the contact plugs [P2]. Any defect, void, or resistive interface introduced during contact formation propagates directly into Metal 0 continuity and pixel readout fidelity [T2].

Entry State and Sequence Logic

Upstream Dependencies

The contact module enters after the PMD deposition and planarization sequence has been completed (Engineering Practice). The 40nm BSI CMOS Image Sensor pre-metal dielectric integration process flow delivers a dielectric stack whose composition and topography directly influence contact etch depth uniformity [P2]. Because the PMD thickness varies over active regions versus gate stacks, the contact etch must contend with non-uniform dielectric depths, requiring highly selective etch chemistries or additional mask levels to avoid over-etching shallow regions while under-etching deep ones [T1].

The silicide strategy chosen upstream also constrains the contact module [P1]. In the 40nm BSI CMOS Image Sensor, a silicide-last integration is commonly adopted in pixel regions, meaning the titanium silicide (TiSiₓ) is formed during the contact module itself by depositing and annealing a titanium/titanium nitride (Ti/TiN) barrier stack [P1]. This differs from standard logic flows where silicidation is completed in the FEOL (Engineering Practice). The silicide-last approach minimizes metal proximity to photodiodes but introduces additional surface preparation challenges during contact formation [P2].

Sequence Within the Module

The CONTACT module process flow follows a logical sequence: lithographic patterning of contact holes, dielectric etch, post-etch residue removal, in-situ pre-clean of the exposed silicon surface, barrier metal deposition, and metal fill [A2]. Each step has a defined entry condition set by the preceding step (Engineering Practice). The lithography step must align to underlying device features with sufficient overlay tolerance; the etch must stop cleanly on silicide or silicon; the pre-clean must remove native oxide without damaging the substrate; and the metal fill must be conformal enough to avoid voiding in high-aspect-ratio vias [T1][P1].

The Metal 0 Gate and S/D Contact Opening - Photo integration principles govern the first step of this sequence [P2]. This photolithographic step defines the spatial pattern of contact holes using krypton fluoride (KrF) lithography, which remains relevant at the 40nm generation for contact-level patterning when supplemented by resolution enhancement techniques [P3]. The photo step must simultaneously define contacts to gate electrodes, source/drain regions, and any local interconnect structures, each at different dielectric depths [P2].

Physical and Chemical Mechanisms

Lithographic Patterning and Resist Flow

The contact hole lithography step at the 40nm node faces fundamental optical diffraction limits [P3]. KrF lithography, operating at its characteristic exposure wavelength, produces aerial images whose contrast diminishes for features approaching the resolution boundary [P3]. To extend the practical resolution, a resist flow process (RFP) can be employed: after exposure and development, a thermal treatment drives the photoresist polymer above its glass transition temperature, causing viscoelastic flow that shrinks the contact hole inward [P3]. Crosslinkable functional groups within the resist simultaneously undergo thermally activated crosslinking, which stabilizes the polymer network and prevents excessive deformation [P3].

The physics underlying RFP rests on polymer chain mobility [P3]. Below the glass transition temperature, polymer segments are locked in a glassy state with negligible flow [P3]. Above it, segments acquire sufficient thermal energy to undergo cooperative motion, and the resist profile relaxes under surface tension and gravitational forces [P3]. The crosslinking reaction progressively increases molecular weight and network density, counteracting further flow and locking the shrunken profile in place [P3]. The interplay between flow kinetics and crosslinking kinetics determines the final critical dimension (CD) and profile shape [P3].

This mechanism is directly relevant to 40nm contact formation because it allows KrF-based patterning to achieve effective CDs below what the optical projection system alone could resolve, without requiring more advanced exposure tools [P3]. The trade-off is that the shrinkage magnitude depends on the initial CD, and the process window for the thermal treatment is narrow [P3].

Dielectric Etch Chemistry

After patterning, the contact holes are transferred into the PMD stack by anisotropic plasma etching [A2]. Fluorocarbon-based chemistries are commonly used, where polymerizing etch gases deposit fluorocarbon polymer on sidewalls to provide profile control while ion bombardment drives vertical etching at the hole bottom [T1]. The etch must contend with varying dielectric thicknesses: over gates the PMD may be thicker, while over source/drain regions it may be thinner [P2]. Simultaneous etching through all depths requires high selectivity to the underlying silicide or silicon to prevent over-etch damage in shallow regions [T1].

Residue generation during etch is a major concern [P1]. Organic fluorocarbon polymers coat the sidewalls and bottom of contact holes, and inorganic residues from resputtered silicon dioxide (SiO₂) can redeposit on exposed surfaces [P1]. These residues must be removed before metal deposition because they act as barrier layers that increase contact resistance [T1].

Pre-Clean and Native Oxide Removal

Before barrier metal deposition, the exposed silicon or silicide surface at the contact bottom must be cleaned of native oxide and organic contaminants [P1]. Conventional argon (Ar) plasma sputter etching can physically remove these layers, but it introduces lattice damage in n-type silicon, which degrades contact resistance and reliability [P1]. The Siconi™ dry chemical clean offers an alternative: a remote plasma generates ammonium fluoride (NH₄F) reactive species that selectively react with SiO₂ to form volatile ammonium fluorosilicate salts, which are subsequently removed by sublimation [P1].

The combined Ar plasma + Siconi™ approach exploits complementary mechanisms [P1]. Ar plasma first removes organic residues and partially reduces oxide through physical bombardment [P1]. The Siconi™ step then chemically removes the remaining native oxide without ion bombardment damage [P1]. The selectivity arises because fluorine-containing reactions attack SiO₂ preferentially over silicon, and the remote plasma configuration minimizes ion flux to the wafer surface [P1]. Temperature control governs the kinetics of both salt formation and sublimation: insufficient thermal energy leaves non-volatile salt residues, while excessive thermal energy can alter the etch rate and CD [P1].

Contact Resistance Physics

The fundamental physics of metal-silicon contact resistance is governed by the Schottky barrier height at the interface [T2]. When a metal contacts silicon, the difference in work functions creates a potential barrier that impedes carrier flow [T1]. For heavily doped silicon, quantum mechanical tunneling through the thin barrier dominates, and contact resistance decreases with increasing doping concentration [T2]. The built-in potential of the junction, determined by the doping levels on both sides, sets the barrier height [T2].

In the 40nm BSI CMOS Image Sensor, contact resistance is particularly critical because pixel readout circuits operate at low signal levels [P2]. Any excess series resistance at the source follower or transfer gate contact degrades conversion gain and increases readout noise [P2]. The silicide contact acts to lower the effective barrier by creating a low-barrier-height interface between the metal and the heavily doped silicon beneath the silicide [P1].

Interfaces and Failure Propagation

Lithography-to-Etch Interface

The contact hole CD defined by lithography directly determines the post-etch via dimension [P3]. If the resist flow process over-shrinks the hole, the resulting narrow via restricts metal fill and increases resistance [P3]. If it under-shrinks, adjacent contacts may merge after etch, creating shorts [P3]. The lithography-to-etch transfer fidelity also depends on the resist profile: a re-entrant or bowed profile transfers into the dielectric as an irregular via shape that is difficult to fill conformally [P3].

Etch-to-Clean Interface

After dielectric etch, the condition of the exposed surface at the contact bottom determines the effectiveness of the subsequent pre-clean [P1]. If etch residues are tenacious or if the etch has damaged the underlying silicide, the pre-clean must work harder, increasing the risk of substrate damage or CD enlargement [T1][P1]. Conversely, an insufficient pre-clean leaves native oxide that blocks silicide formation during the subsequent anneal, resulting in high contact resistance [P1].

The interaction between etch and clean also affects CD control [P1]. The Siconi™ process can cause CD swelling due to salt formation within the contact hole, which must be balanced against the need for thorough oxide removal [P1]. The sequence of Ar plasma followed by Siconi™ is specifically engineered to minimize this trade-off: the Ar step reduces the oxide thickness that Siconi™ must process, thereby limiting salt generation and CD swelling [P1].

Clean-to-Metal Deposition Interface

The pre-clean leaves the silicon surface in a chemically active state that is prone to re-oxidation [P1]. The time between pre-clean and barrier metal deposition must be minimized to prevent native oxide regrowth [P1]. In the silicide-last integration, titanium is deposited directly onto the cleaned silicon surface and then annealed to form TiSiₓ [P1]. The quality of this silicide depends critically on the interfacial chemical state: residual oxide, carbon, or fluorine contaminants inhibit silicide nucleation and produce high-resistance or discontinuous silicide films [P1][T1].

Downstream Failure Propagation

Failures in the contact module propagate into multiple downstream effects (Engineering Practice). High contact resistance increases the source follower resistance in pixel circuits, reducing the signal-to-noise ratio and degrading image quality [P2]. Contact voids or incomplete fill create reliability risks under electromigration stress [A2]. In the 40nm BSI CMOS Image Sensor, where the backside illumination architecture demands thin device stacks, contact failures cannot be compensated by additional interconnect levels [P1].

The contact pad structures in BSI sensors introduce additional failure modes [A2]. Raised contact pad topography can interfere with subsequent microlens formation, distorting the optical path [A2]. Non-photosensitive resin fill and planarization techniques have been developed to mitigate this issue by leveling the surface before optical layer deposition [A2].

Walk the Real Module

To explore the actual step-by-step sequence of the 40nm BSI CMOS Image Sensor contact formation process flow, you can Open CONTACT Step 112 in the interactive flow [T1]. This interactive module walks through each process step in order, showing the entry conditions, processing actions, and exit deliverables that define the contact formation sequence (Engineering Practice).

The interactive flow illustrates how the Metal 0 Gate and S/D Contact Opening - Photo step fits within the broader CONTACT module process flow, preceded by PMD planarization and followed by etch, clean, and metal fill steps [P3]. By stepping through the sequence, you can observe the integration logic that governs how each step's output constrains the next step's process window (Engineering Practice).

For the broader context of where contact formation sits within the complete 40nm BSI CMOS Image Sensor process flow, refer to the 40nm BSI CMOS Image Sensor process flow overview, which maps the full module sequence from device isolation through final metallization [P2].

Related Learning Paths

Engineers studying contact formation should explore several adjacent modules to build a complete integration picture:

• The pre-metal dielectric module directly feeds the contact etch and determines the dielectric landscape through which contacts must be etched [A2]. Understanding PMD material selection, deposition conformality, and planarization strategy is essential for predicting contact etch uniformity [A2]. Refer to the PMD integration process flow article for this context [P2].

• The Metal 0 interconnect module consumes the contact module's output (Engineering Practice). The contact plug tops must be planarized and exposed sufficiently for Metal 0 landing pad patterning [A2]. The Metal 0 interconnect integration article covers the downstream requirements [T1].

• For engineers interested in the optical and device physics side, the photodiode design and floating diffusion optimization literature [P2] provides insight into why contact placement and metal proximity matter so much for sensor performance. The trade-off between contact density and optical fill factor is a recurring theme in BSI CMOS image sensor design [P2].

• From a device physics perspective, the metal-semiconductor junction theory [T2] and semiconductor band structure fundamentals [T3] provide the theoretical grounding for understanding why contact resistance scales with doping, barrier height, and interface quality.

• Emerging transistor architectures such as gate-all-around (GAA) and nanosheet structures introduce new contact formation challenges, including suspended source/drain regions and backside contact schemes [A1]. While these are beyond the 40nm planar CIS domain, they represent the direction in which contact module complexity is evolving [P3].

Future Outlook

The 40nm BSI CMOS Image Sensor contact formation process reflects a mature but evolving integration scheme [P2]. As pixel sizes continue to shrink and stacked sensor architectures gain adoption, contact formation will face increasing aspect ratios, tighter pitch constraints, and more stringent silicide uniformity requirements [P3]. The trend toward three-dimensional integration, where the pixel array and signal processing circuitry are fabricated on separate wafers and bonded, may shift contact formation from intra-wafer to inter-wafer bonding interfaces, changing the defect spectrum and reliability paradigms [T2].

Advanced pre-clean technologies, including remote plasma and selective chemical etch approaches, will continue to displace purely physical sputter cleans as device dimensions shrink and lattice damage tolerance decreases [P1]. The integration of novel barrier metals beyond Ti/TiN, such as cobalt or ruthenium-based liners, is another direction that may alter the contact resistance landscape [A2]. Finally, the intersection of contact formation with backside illumination and through-silicon via (TSV) technology in stacked sensors will require contact modules that can operate on thinned, bonded substrates with different mechanical and thermal constraints than conventional frontside processing [A1].