40nm BSI CMOS Image Sensor Third Interlayer Dielectric Integration: Process Flow Principles and Device Physics

Role in the Complete Flow

The third interlayer dielectric (ILD3) module in a 40nm BSI CMOS Image Sensor occupies a pivotal position within the back-end-of-line (BEOL) interconnect stack [P3]. Upstream, it receives a fully patterned metal-two and via-two interconnect level—meaning the second-level copper or aluminum metallization has already been deposited, planarized by chemical mechanical polishing (CMP), and cleaned [P4]. The ILD3 module must then deposit a sequence of dielectric films that serve simultaneously as electrical insulation, copper diffusion barriers, etch-stop layers for subsequent patterning, and mechanical stress buffers [T1].

Downstream, the ILD3 module must deliver a highly planarized, defect-free dielectric surface ready for metal-three trench and via-three patterning [P3]. In a 40nm BSI CMOS Image Sensor, this requirement is amplified by the unique architecture: the front-side interconnect stack must later serve as a reflector and crosstalk-suppression structure when viewed from the backside after substrate thinning [P2]. The dielectric stack quality directly influences optical crosstalk, metal reflectivity for photogenerated carriers, and ultimately quantum efficiency [P1]. Furthermore, because the 40nm BSI CMOS Image Sensor employs a pinned photodiode (PPD) architecture, any mobile ions or process-induced charges that penetrate through the interconnect dielectric stack can alter the surface potential at the photodiode and increase dark current [P1][P4]. The ILD3 module therefore acts as both a structural platform for the next metal level and a guardian of pixel electro-optical integrity [P3].

The ILD3 module also plays a critical role in hydrogen management (Engineering Practice). In advanced three-dimensional CMOS image sensor (3D-CIS) fabrication, multi-dielectric films combined with metallic wiring create a hydrogen diffusion barrier that prevents hydrogen from reaching pixel active regions during forming gas annealing [P4]. The ILD3 deposition integration principles must therefore account for how subsequent dielectric and metal layers will either facilitate or block hydrogen passivation of interface states at shallow trench isolation (STI), deep trench isolation (DTI), and bonding interfaces [P4].

Entry State and Sequence Logic

The entry state for the ILD3 module is defined by the completion of the second metal level within the broader 40nm BSI CMOS Image Sensor process flow [P3]. At this point, the wafer surface presents exposed metal-two conductors embedded in the prior ILD2 dielectric, with the top surfaces co-planarized by CMP [T1]. The sequence logic demands that any residual copper slurry, particulate contamination, or native oxide on the metal surfaces be removed before dielectric deposition begins, because even trace metallic contamination can diffuse through subsequent dielectric layers and create deep-level traps in the pixel photodiode region [P4].

The ILD3 module process flow typically follows a sub-layer sequence: first, a thin barrier or etch-stop layer (often silicon carbonitride, SiCN) is deposited; second, a bulk dielectric fill layer is deposited to achieve the required interlevel spacing; third, CMP planarization brings the surface to the target topography; and finally, a post-CMP clean removes residual slurry and prepares the surface for the next lithography step [P3]. The SiCN layer serves dual purposes: it acts as a copper diffusion barrier preventing metal migration into the bulk dielectric, and it functions as a selective etch-stop during subsequent metal-three trench patterning [A1].

The sequence ordering is governed by several integration dependencies (Engineering Practice). The SiCN barrier must be deposited immediately after metal-two surface preparation to prevent copper oxidation and ambient contamination [P4]. The bulk dielectric deposition that follows must be capable of gap-filling narrow spaces between metal-two features without forming voids or seams, which requires careful selection of deposition technique—plasma-enhanced chemical vapor deposition (PECVD), sub-atmospheric chemical vapor deposition (SACVD), or high-density plasma chemical vapor deposition (HDPCVD) each offer different gap-fill and stress characteristics [T1]. If the bulk dielectric is deposited under conditions that induce excessive tensile or compressive stress, the cumulative mechanical stress can propagate downward through the interconnect stack and cause dielectric cracking, metal delamination, or even displacement of the photodiode junction [T1][A1].

Critically, the ILD3 sequence must also be compatible with the overall thermal budget of the 40nm BSI CMOS Image Sensor [P3]. Because the sensor employs a pinned photodiode with carefully engineered doping profiles—including a high-concentration p+ surface layer with a steep gradient—any high-temperature step in the BEOL can cause dopant redistribution that degrades the electric field distribution at the photodiode surface [P1]. The ILD3 deposition temperatures must therefore remain sufficiently low to preserve the front-end-of-line (FEOL) junction integrity while still producing dense, high-quality dielectric films [T1].

Physical and Chemical Mechanisms

Dielectric Deposition Chemistry

The bulk of the ILD3 dielectric is typically silicon dioxide (SiO₂) deposited by CVD techniques using precursors such as silane or tetraethylorthosilicate (TEOS) [T1]. In plasma-enhanced deposition, the precursor molecules are dissociated by radio-frequency plasma energy, generating reactive radical species that adsorb onto the wafer surface and polymerize into a Si-O-Si network [T1]. The polymerization reaction releases water as a byproduct, which must be driven off through thermal treatment to densify the film and reduce moisture content [T1]. Incomplete densification leaves the film porous and susceptible to chemical attack, which can compromise dielectric integrity and introduce mobile ionic contamination [P4].

For HDPCVD deposition, the simultaneous deposition and sputter-etching mechanism provides superior gap-fill in narrow features [P4]. Ion bombardment from the high-density plasma simultaneously densifies the growing film and redistributes material from feature corners into gaps, preventing the formation of overhang structures that would create voids [T1]. This mechanism is particularly important at the 40nm node, where metal-two pitch scaling creates narrow, high-aspect-ratio gaps that challenge conventional deposition techniques [P4].

SiCN Barrier Layer Physics

Silicon carbonitride (SiCN) is employed as the ILD3-1 barrier layer due to its unique combination of properties [T1]. The incorporation of carbon into the silicon nitride matrix modifies the film's bond structure, reducing both dielectric constant and internal stress compared to pure silicon nitride [P4]. From a device physics perspective, SiCN acts as an effective copper diffusion barrier because its dense amorphous network restricts interstitial copper migration [A1]. The layer also functions as a selective etch-stop: during metal-three trench etching, the plasma chemistry can be tuned to etch the bulk oxide selectively while stopping on the SiCN surface, providing self-aligned depth control [P3].

The SiCN layer also influences the optical path in a BSI sensor [P1]. Because the front-side metallization can serve as a reflector for boosting quantum efficiency [P2], the refractive index and thickness of each dielectric layer in the stack—including the SiCN barrier—participate in determining the optical stack reflectance. A poorly optimized SiCN layer can create unintended interference effects that reduce the reflectivity of the metal layers at wavelengths of interest for the sensor's spectral response [P1].

Planarization Mechanisms

CMP planarization of the ILD3 dielectric relies on the synergistic action of chemical dissolution and mechanical abrasion [T1]. The slurry chemistry selectively softens the oxide surface through hydration reactions, while the abrasive particles in the slurry mechanically remove the softened material (Engineering Practice). The polish pad's relative motion creates a pressure distribution that preferentially removes material from high-topography regions, driving the surface toward global planarity [T1]. The quality of planarization directly affects the depth uniformity of subsequently etched metal-three trenches—non-planarity translates into across-wafer variation in trench depth, which can cause interlevel short circuits or open circuits [A2].

Stress and Hydrogen Diffusion Interactions

The mechanical stress state of the ILD3 stack has far-reaching consequences [P4]. Tensile stress in the dielectric can crack the film, while compressive stress can cause wafer warpage and misalignment in subsequent photolithography steps [T1]. More subtly, the stress state at the Si/SiO₂ interface influences the density of interface states (Dit), which act as generation-recombination centers [P4]. In the 40nm BSI CMOS Image Sensor, elevated Dit at STI and DTI interfaces directly increases dark current and white pixel defects [P1]. The ILD3 dielectric stack, being part of the multi-dielectric film sequence above the pixel region, can block hydrogen from diffusing to these interfaces during forming gas annealing [P4]. This hydrogen diffusion barrier effect means that interface state passivation must be addressed through wafer-level engineering—such as hydrocarbon molecular ion implantation that embeds hydrogen within the epitaxial layer—rather than relying solely on post-deposition annealing [P4].

Interfaces and Failure Propagation

Metal-Dielectric Interface

The interface between the metal-two conductor and the ILD3-1 SiCN barrier is a critical reliability node [T1]. Poor adhesion at this interface can lead to delamination during subsequent thermal cycles or CMP processing [P4]. The SiCN barrier must form a continuous, pinhole-free film over the metal surface; any discontinuity provides a pathway for copper diffusion into the bulk dielectric, which can create leakage paths between adjacent metal lines and, in the worst case, contaminate the pixel active region [P4]. Copper contamination is particularly insidious in CMOS image sensors because copper acts as a fast-diffusing interstitial impurity in silicon, introducing deep-level traps that increase dark current and degrade charge transfer efficiency [P4].

Dielectric-Dielectric Interface

The interface between the SiCN barrier and the bulk oxide fill must also be mechanically and chemically robust [T1]. During CMP, the polish slurry can penetrate weakly bonded interfaces and cause delamination (Engineering Practice). Additionally, if the SiCN surface is exposed to ambient atmosphere between the ILD3-1 deposition and the bulk oxide deposition steps, moisture absorption and native oxidation can create a contaminated interface that degrades adhesion and dielectric strength [P1]. In-situ or sequential deposition strategies mitigate this risk by minimizing the exposure window [A1].

Downstream Optical Consequences

In a BSI CMOS image sensor, the front-side interconnect dielectric stack is not merely an electrical insulator—it is part of the optical path [P1]. After backside thinning, incident light passes through the thinned silicon substrate, reaches the photodiode, and any unabsorred photons continue through to the front-side dielectric and metal stack [P2][A2]. The reflectivity of this stack determines how many photons are reflected back into the photodiode for a second absorption opportunity [P1]. The ILD3 dielectric's refractive index, combined with the SiCN barrier's optical properties, creates a multilayer interference structure [P3]. If the dielectric stack is not optically optimized, destructive interference at specific wavelengths can reduce reflectivity and lower quantum efficiency, particularly in the near-infrared (NIR) regime where silicon absorption is weak and photons may traverse the full epitaxial layer thickness [P1].

Stress-Induced Dark Current

The mechanical stress transferred from the ILD3 stack to the underlying silicon substrate can deform the crystal lattice near STI and DTI edges, enhancing generation-recombination current at these interfaces [T1]. This mechanism is especially relevant for small-pixel 40nm BSI CMOS Image Sensors, where the DTI isolation is in close proximity to the photodiode [P2]. The direction of the tradeoff is clear: harder, denser dielectric films provide better gap-fill and barrier properties but transfer more stress to the silicon, potentially increasing dark current [P1]. Conversely, softer, lower-stress films reduce mechanical impact but may compromise barrier integrity and gap-fill capability (Engineering Practice).

Cumulative Thermal Budget Effects

Each deposition and annealing step in the ILD3 module adds to the cumulative thermal budget experienced by the FEOL structures (Engineering Practice). In the 40nm BSI CMOS Image Sensor, the pinned photodiode's doping profile—including the high-concentration p+ surface layer and the deliberately reduced doping concentration at the p+/n junction—must be preserved throughout all BEOL processing [P1]. Excessive thermal exposure can broaden these carefully engineered junctions, weakening the surface drift electric field that enables efficient ultraviolet carrier collection and potentially increasing generation-recombination dark current at the junction [P1]. The ILD3 module's thermal contribution must therefore be balanced against the remaining BEOL thermal budget allocated for metal-three and subsequent interconnect levels (Engineering Practice).

Walk the Real Module

To observe the actual ILD3 integration steps within the 40nm BSI CMOS Image Sensor flow, you can Open ILD3 Step 193 in the interactive flow [P3]. This step represents the entry point into the ILD3 deposition sequence, where the wafer has completed metal-two and via-two processing and is prepared for the first ILD3 sub-layer deposition [P3].

The walkthrough of the real module proceeds qualitatively as follows:

Step 1 — Post-metal-two surface preparation: The wafer enters with a planarized metal-two surface [A2]. A cleaning step removes CMP residue, particulates, and native oxide from exposed metal surfaces (Engineering Practice). This step is critical because any residual copper or slurry particles will become embedded under the ILD3 dielectric and cannot be removed afterward [P4].

Step 2 — ILD3-1 SiCN barrier deposition: A thin SiCN film is deposited conformally over the entire wafer surface [T1]. The deposition must achieve complete coverage of metal-two sidewalls and bottom surfaces [A1]. The carbon content and nitrogen stoichiometry are tuned to balance copper diffusion barrier performance against optical transparency and mechanical stress [A1].

Step 3 — Bulk ILD3-2 oxide deposition: The main dielectric layer is deposited using a CVD technique selected for gap-fill capability at the 40nm metal-two pitch [T1]. The deposition chemistry may employ TEOS-based or silane-based precursors, with the plasma parameters adjusted to achieve the desired film density, stress, and moisture content [T1]. For narrow gaps between metal-two lines, HDPCVD's simultaneous deposition-sputter mechanism may be employed to prevent void formation [P4].

Step 4 — CMP planarization: The bulk oxide is polished back to achieve the target ILD3 topography [A2]. The polish endpoint may be detected by optical or motor-current monitoring (Engineering Practice). Post-CMP, the surface should exhibit minimal dishing over large metal features and minimal erosion in dense pattern regions [P4].

Step 5 — Post-CMP cleaning and inspection: Residual slurry particles and chemical contaminants are removed (Engineering Practice). The wafer is inspected for scratches, voids, and particulate defects (Engineering Practice). The cleaned, planarized surface is then ready for the 40nm BSI CMOS Image Sensor metal-three interconnect integration process flow, which will pattern trenches into the ILD3 dielectric and deposit the metal-three conductors [P3].

The 40nm BSI CMOS Image Sensor via-three integration process flow follows metal-three, completing the third interconnect level [P3].

Related Learning Paths

Engineers studying the ILD3 module should connect it to several adjacent topics within the 40nm BSI CMOS Image Sensor process architecture:

• The overarching 40nm BSI CMOS Image Sensor process flow provides the full-module context, showing how ILD3 fits among the FEOL pixel formation, backside thinning, and color filter/microlens fabrication steps [P3].
• The downstream 40nm BSI CMOS Image Sensor metal-three interconnect integration process flow directly consumes the ILD3 output and reveals how trench etch depth control depends on the SiCN etch-stop quality established during ILD3-1 deposition [P3].
• The 40nm BSI CMOS Image Sensor via-three integration process flow further extends the interconnect chain, where via etch selectivity relies on the same ILD3 dielectric properties [P3].

Beyond the 40nm node specifically, engineers should explore how ILD integration principles scale with pixel size reduction, how three-layer stacked CIS architectures introduce additional dielectric-bonding interface challenges [P3], and how wafer-level gettering and hydrogen passivation strategies interact with the BEOL dielectric stack to control dark current and white pixel defects [P4]. The pinned photodiode physics that underpin the entire sensor operation [P2] provide the foundational device physics for understanding why dielectric quality matters so profoundly in image sensor fabrication.

Future Outlook

The evolution of CMOS image sensors toward smaller pixels, higher dynamic range, and three-dimensional stacking is driving several emerging trends in ILD integration [P3]. First, the adoption of low-dielectric-constant (low-k) materials in the BEOL stack is gaining traction to reduce parasitic capacitance between interconnect levels, which improves signal readout speed and reduces power consumption [P3]. However, low-k materials typically exhibit higher porosity and lower mechanical strength, creating tension with the gap-fill and stress-management requirements that are already challenging at the 40nm node (Engineering Practice).

Second, three-layer stacked CIS architectures introduce new dielectric interface challenges at the bonding plane [P3]. The dielectric stack above the pixel array must be compatible with hybrid bonding surfaces, requiring ultra-low surface roughness and controlled dielectric thickness to ensure reliable Cu-Cu direct bonding [P1]. This may drive the adoption of chemical mechanical planarization with tighter endpoint control or the introduction of specialized bonding-compatible dielectric cap layers [P4].

Third, the hydrogen diffusion barrier problem identified in multi-dielectric BEOL stacks [P4] is motivating research into alternative passivation strategies. Hydrocarbon molecular ion-implanted epitaxial wafers that embed gettering sites and hydrogen sources within the epitaxial layer itself represent one promising direction, but their compatibility with progressively lower thermal budgets remains an open question [P4]. As BEOL dielectric stacks become more complex with additional metal levels, the challenge of delivering hydrogen to pixel active interfaces will intensify [P4].

Finally, as BSI sensors push toward wider spectral response—extending into both the ultraviolet and near-infrared regimes [P1]—the optical properties of every layer in the front-side dielectric stack become part of the sensor design space. The ILD3 module, with its SiCN barrier and bulk oxide layers, may need to be co-optimized as an optical interference structure rather than treated purely as an electrical insulator [P1]. This convergence of optical and electrical engineering in dielectric integration represents one of the most intellectually stimulating frontiers in CMOS image sensor process development [P1].