40nm BSI CMOS Image Sensor Via 3 Lithography: Integration Principles and Device Physics

Role in the Complete Flow

In the 40nm Backside Illumination (BSI) CMOS Image Sensor (CIS) backend-of-line (BEOL) fabrication flow, the Via 3 Lithography (VIA 3 - Photo) step serves as a critical pattern-definition module. Positioned immediately following the deposition of the dual-dielectric stack (ILD 3-2 and ILD 3-1), this lithographic operation selectively defines the spatial positions of vertical interconnect vias. In advanced image sensors, CMOS technology enables high functional integration within each pixel by leveraging standard semiconductor scaling [T2]. Within this multi-level metallization scheme, Via 3 establishes vertical electrical conduits that connect underlying Metal 3 routing lines to the overlying Metal 4 layer.

At this stage of the 40nm BSI CMOS Image Sensor process flow, front-end-of-line (FEOL) devices—including pinned photodiodes (PPD) and pixel transistors (reset, transfer, source follower, and row select)—are fully formed and covered by intermediate lower-level interconnect tiers. The VIA 3 - Photo step establishes the sacrificial polymer mask required to carve high-aspect-ratio openings through the ILD 3 stack. Because BSI image sensors require wafer flipping, back-surface substrate thinning, and optical passivating after BEOL processing, the structural fidelity of every front-side via pattern directly impacts device yield and long-term mechanical reliability.

From a device physics standpoint, Via 3 interconnects form part of the readout signal path. In a CIS pixel, photogenerated electrons collected in the photodiode are transferred to the floating diffusion (FD) node. Parasitic capacitance contributed by improper via geometries, misalignment, or dielectric damage reduces pixel conversion gain. Therefore, Via 3 patterning must maintain rigorous critical dimension (CD) control and precise overlay to ensure low contact resistance and low parasitic capacitive coupling.

Entry State and Sequence Logic

Integration Dependencies Before V3

Prior to Via 3 lithography, the wafer state consists of patterned Metal 3 copper or aluminum conductors embedded in planarized dielectric, capped by an etch-stop dielectric liner (ILD 3-1, such as silicon carbon nitride, SiCN) and a primary interlayer dielectric (ILD 3-2, such as silicon dioxide or fluorinated oxide). The ILD 3 surface is planarized using chemical mechanical polishing (CMP) to present a flat baseline for optical photolithography.

The integration sequence demands that all high-thermal-budget operations—such as source/drain dopant activation anneals—be completed in FEOL. BEOL processing operates under strict thermal budget limits to prevent metal line electromigration, interdiffusion, and dopant redistribution in the underlying PPD. The PPD surface p+ pinning layer suppresses dark current originating from interface states. Any uncalibrated thermal spike during BEOL dielectric processing or post-exposure bakes risks broadening this shallow p+ profile, deteriorating surface pinning and increasing dark noise.

Downstream Delivery Requirements

VIA 3 - Photo delivers a developed photoresist template containing clean, patterned via openings over designated Metal 3 landing pads. This template acts as the etch mask for subsequent dry etching steps that transfer the pattern into the ILD 3-2 oxide and ILD 3-1 dielectric liner.

Following pattern transfer and resist stripping, the opened vias undergo barrier metal deposition, seed layer formation, and metal plug fill, leading directly to third interlayer dielectric integration and subsequent metal-four interconnect integration. Vertical interconnects establish electrical conduction across different metallization planes within multi-level interconnect networks [A1]. If Via 3 lithography suffers from pattern distortion, critical dimension blooming, or overlay misalignment, downstream etch steps propagate these errors, resulting in elevated contact resistance, via unlanding, or inter-line dielectric breakdown.

Physical and Chemical Mechanisms

Photolithographic Pattern Transfer

The VIA 3 - Photo process employs 193-nm immersion lithography (193i) or advanced dry 193-nm photolithography to achieve the dense pitch and sub-micron resolution required at the 40nm node. An anti-reflective coating (ARC) is applied beneath a positive chemically amplified photoresist (CAR) to absorb back-reflected light from underlying metal layers, eliminating standing wave artifacts and substrate reflectivity interference.

During exposure, 193-nm photons illuminate the photoresist through a photomask. Photoacid generators (PAGs) within the exposed resist regions absorb photon energy and generate acid catalysts (H+). During the post-exposure bake (PEB), these acid molecules catalytically cleave lipophilic protecting groups on the polymer binder, converting hydrophobic polymer chains into hydrophilic carboxylic acid groups:

R-COOR' + H+ -> R-COOH + R'' + H+

This catalytic deprotection reaction drastically increases polymer solubility in aqueous alkaline developers (such as tetramethylammonium hydroxide, TMAH). The exposed resist is selectively dissolved during development, yielding vertical sidewall profiles that expose the underlying ILD 3-2 surface.

To compensate for optical diffraction effects at small feature pitches, Optical Proximity Correction (OPC) is applied to the mask layout. Sub-resolution assist features (SRAFs) and mask biasing modify the aerial image, ensuring that the light intensity profile at the wafer surface produces circular via holes with uniform critical dimensions across both isolated and dense arrays.

Dielectric Etch Chemistry and Pattern Propagation

Once the resist template is finalized, anisotropic plasma etching transfers the pattern into the dielectric stack. Etching is performed in fluorocarbon-based chemistries (CF4, C4F8, Ar, and O2). Fluorocarbon radicals chemically react with silicon dioxide to form volatile SiF4 and CO2 byproducts, while accelerated argon ions provide physical sputtering momentum to maintain vertical sidewall anisotropy.

The etch stops on the ILD 3-1 SiCN capping layer, which provides chemical selectivity relative to the bulk oxide. A secondary etch step subsequently clears the SiCN liner to expose the underlying Metal 3 landing pad without excessively sputtering the conductive metal.

Via Metallization and Planarization

Following pattern etch, photoresist and organic residues are removed using oxygen plasma ashing and specialized solvent cleans. A conformal diffusion barrier (such as Ti/TiN or Ta/TaN) is deposited via atomic layer deposition (ALD) or physical vapor deposition (PVD) to prevent metal atom migration into the surrounding low-k or oxide dielectric. Subsequent metallization steps depend on dielectric and via integrity, where deposition and post-processing parameters govern film properties such as stress, adhesion, and resistivity [P2]. Metal fill (tungsten or copper) is deposited into the via cavity, followed by CMP planarization to isolate individual vertical via plugs.

Interfaces and Failure Propagation

Via-Metal Interface Quality

The physical interface between the base of Via 3 and the underlying Metal 3 pad governs vertical contact resistance. If Via 3 lithography leaves undeveloped resist scum or if the post-etch clean fails to remove fluorocarbon polymer residues, a high-resistance barrier forms at the interface. In pixel array readout circuits, fluctuating contact resistance manifests as column fixed-pattern noise (FPN) and reduced signal-to-noise ratio (SNR).

Dielectric Integrity and Cross-Talk

Overlay misalignment between the Via 3 pattern and underlying Metal 3 lines reduces the landing area margin. Unlanded or partially landed vias force the subsequent dielectric etch to penetrate adjacent inter-metal dielectric regions. This localized thinning of the ILD increases inter-line leakage currents and elevates parasitic capacitive coupling between neighboring pixel signal paths, exacerbating optical and electrical cross-talk.

Thermal Budget and PPD Preservation

Although BEOL lithography operates at ambient temperature, subsequent PEB and dielectric curing steps contribute to the cumulative thermal exposure of the wafer. Excessive thermal exposure risks driving dopant diffusion at the PPD p-n junctions. Maintaining a steep doping gradient at the p+ surface pinning layer is vital for maintaining the electric drift field that collects photogenerated electrons; thermal broadening of this junction leads to dark current spikes and reduced quantum efficiency.

Backside Illumination Considerations

In BSI architectures, after the completion of all BEOL layers, the wafer is bonded to a carrier handle wafer and thinned from the backside to expose the silicon photodiode array. Mechanical forces generated during grinding and chemical-mechanical polishing induce stress across the front-side BEOL interconnect stack. Poor adhesion at lithographically defined via interfaces or structural voids inside Via 3 plugs can initiate micro-cracks or delamination under grinding strain, destroying functional readout chains.

Packaging Interface

During final packaging, image sensor dies undergo wire bonding or through-silicon via (TSV) integration alongside color filter and micro-lens arrays. Thermomechanical stresses induced during thermal cycling concentrate at mechanical interfaces within the multi-level metallization stack. Properly dimensioned and defect-free Via 3 structures mitigate localized stress concentration, preventing dielectric cracking during package reliability testing.

Walk the Real Module

To inspect the sequential steps of this module in context, explore the interactive VIA 3 - Photo step detail.

In the physical process sequence, Via 3 patterning begins with spin-coating a bottom anti-reflective coating (BARC) and chemically amplified positive photoresist onto the planarized ILD 3 surface. The wafer enters the 193-nm immersion scanner where mask alignment targets align the Via 3 pattern to underlying Metal 3 alignment keys. Exposure projects the aerial image onto the resist layer, creating localized acid distributions. A post-exposure bake completes the polymer deprotection reaction, followed by developer dispense and rinse to open the via patterns.

Inspection tools measure critical dimension uniformity (CDU) and overlay errors across the wafer. If overlay or CD metrics exceed strict process windows, the resist layer can be stripped and reworked before irreversible dielectric etching occurs. Once validated, the wafer moves to anisotropic plasma etching, liner clearing, polymer ashing, barrier/seed deposition, metal fill, and CMP planarization.

Related Learning Paths

To build a comprehensive understanding of interconnect integration in image sensors, engineers should explore these complementary modules:

• 40nm BSI CMOS Image Sensor Process Flow: Overview of the entire fabrication sequence from photodiode formation to backside optics.
• 40nm Third Interlayer Dielectric Integration Process Flow: Detailed analysis of ILD 3-1 and ILD 3-2 film deposition, stress tuning, and planarization prior to Via 3 photo.
• 40nm Metal-Four Interconnect Integration Process Flow: Integration of the overlying metallization tier that lands directly on the completed Via 3 plugs.

Future Outlook

As CMOS image sensor pixel pitches scale toward sub-micron dimensions, traditional single-exposure 193i Via 3 lithography faces physical resolution limits imposed by optical diffraction. Advanced nodes increasingly adopt Self-Aligned Via (SAV) schemes or Extreme Ultraviolet (EUV) lithography to eliminate overlay error margins and maintain vertical via fidelity without aggressive mask biasing.

Furthermore, 3D wafer-to-wafer hybrid bonding architectures are shifting traditional BEOL signal routing responsibilities to direct copper-to-copper dielectric interfaces. In these stacked sensor designs, Via 3 patterning plays a crucial role in managing inter-tier power distribution and high-speed digital logic connectivity while isolating sensitive analog pixel signals from digital switching noise.