40nm BSI CMOS Image Sensor Metal-Four Interconnect Integration: Process Flow Principles and Device Physics

Role in the Complete Flow

In the 40nm backside-illuminated (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor process flow, the metal-four (MET4) interconnect module occupies a pivotal position within the back-end-of-line (BEOL) interconnect stack. This module receives a wafer that has already undergone front-end device formation—including pinned photodiode (PPD) construction, transfer gate integration, and floating diffusion (FD) optimization—as well as the lower metal levels (MET1 through MET3) and their associated interlayer dielectrics. Connections between global interconnect levels are formed through openings in the intermetal dielectrics that separate interconnects from active areas and adjacent metal layers [T1]. In this integration scheme, the MET4 trenches are constructed within the third interlayer dielectric (ILD3) stack above open via-three (Via-3) cavities, establishing horizontal routing pathways linked to the pixel readout transistors.

The MET4 module must deliver a patterned metal interconnect layer that fulfills three concurrent obligations. First, it provides low-resistance horizontal signal routing between pixel arrays and peripheral readout circuitry. Second, it serves as an electromagnetic shielding plane that suppresses crosstalk between sensitive analog pixel signals and noisy digital logic. Third, in BSI configurations, it can act as an optical reflector that redirects unabsorbed photons back into the silicon substrate to boost quantum efficiency (QE). The downstream consumers of MET4 output include the subsequent ILD4 deposition, any additional upper metal levels, and ultimately the passivation and bonding pad formation steps.

In backside-illuminated image sensor configurations, the substrate is thinned down so that incident light entering from the rear of the wafer can be directly absorbed within the photosensitive depletion region [T2]. Because light enters from the backside, frontside metal does not cast shadows on the photodiode but instead can be leveraged as a reflective layer. This fundamentally changes the MET4 design constraints compared to frontside-illuminated sensors, where metal opacity directly blocks photons from reaching the photosensitive region. The 40nm metal-four interconnect integration must therefore balance electrical routing density with optical reflectivity optimization—a duality absent in conventional logic BEOL flows.

Entry State and Sequence Logic

Integration Dependencies

The MET4 module in the 40nm BSI CMOS image sensor sequence depends on the successful completion of several upstream modules. The third interlayer dielectric (ILD3) stack—consisting of an ILD 3-1 SiCN etch-stop layer and ILD 3-2 oxide—must provide adequate dielectric isolation and thickness uniformity. Following Via-3 pattern and etch, the wafer entering the METAL 4 TRENCH - Photo step contains deep, open Via-3 cavities that extend down to underlying Metal 3 landing pads. These open cavities present severe surface topography that must be managed during trench lithography.

Sequence Ordering Rationale

The MET4 module process flow follows a via-first, trench-last dual-damascene sequence grounded in the physical constraints of dual-damascene integration. First, ILD3 is deposited and planarized. Second, Via-3 cavities are patterned and etched into ILD3 down to Metal 3. Third, before applying photoresist for METAL 4 TRENCH - Photo, a sacrificial gap-fill polymer or bottom anti-reflective coating (BARC) is spin-coated across the wafer. This material plugs the open Via-3 cavities and planarizes the surface topography, providing a uniform focal plane for the photoresist while protecting underlying Metal 3 from etch chemistry during subsequent processing. Fourth, krypton fluoride (KRF) lithography patterns the MET4 trench mask. Fifth, the dielectric trench etch defines the MET4 routing channels. Sixth, the gap-fill polymer is stripped, followed by barrier/seed deposition, electrochemical copper deposition (filling both Via-3 and MET4 trenches simultaneously), and chemical mechanical planarization (CMP). This dual-damascene ordering ensures seamless via-to-trench continuity and eliminates intermediate metal CMP steps.

The decision to use KRF lithography for METAL 4 TRENCH - Photo integration reflects a tradeoff between resolution requirements and cost. At the 40nm node, the MET4 pitch is typically more relaxed than critical front-end layers, making KRF lithography sufficient for patterning while maintaining throughput advantages. However, the pixel array region may contain fine-pitch metal grids used for light shielding or reflector patterning, which can push the lithographic requirements closer to the KRF resolution limit and necessitate aggressive optical proximity correction (OPC).

Connection to Adjacent Modules

The MET4 module does not exist in isolation. Its entry state is directly determined by the 40nm BSI CMOS Image Sensor Third Interlayer Dielectric Integration: Process Flow Principles and Device Physics, which governs the dielectric surface quality and thickness uniformity that MET4 trench lithography depends upon. Similarly, the 40nm BSI CMOS Image Sensor Via-Three Integration: Process Flow Principles and Device Physics determines the via-3 profile and cavity depth that MET4 dual-damascene fill must complete. Any defect or non-uniformity introduced in these preceding modules will manifest as MET4 patterning or fill defects, illustrating the tight coupling between successive BEOL sub-modules.

Physical and Chemical Mechanisms

METAL 4 TRENCH - Photo Integration Principles

The METAL 4 TRENCH - Photo step uses photolithographic patterning to define the metal-4 interconnect geometry in photoresist. The principle relies on ultraviolet (UV) exposure of a photosensitive resist through a reticle mask, where the aerial image formed by the optical system modulates the resist solubility through acid-catalyzed deprotection reactions in chemically amplified resists (CARs). For the 40nm BSI CMOS image sensor, KRF lithography generates the aerial image, and the resist development chemistry then transfers the latent image into a three-dimensional resist profile that serves as an etch mask for subsequent ILD 3-2 dielectric trench formation.

The resolution of the MET4 trench pattern is governed by the optical system characteristics and resist chemistry. When trench dimensions approach the lithographic limit of KRF, proximity effects—such as line-end shortening, corner rounding, and iso-dense bias—become significant. These effects arise from the diffusion of photoacid generators (PAGs) within the resist matrix and the partial coherence of the illumination source. In the pixel array region, where metal routing density may be lower but optical uniformity is critical for reflector function, the proximity environment differs substantially from the peripheral circuitry region, where dense interconnect patterns dominate. This spatial variation in pattern density requires careful mask proximity correction (OPC) to maintain consistent trench critical dimensions across both regions.

The photoresist profile quality directly determines the trench etch profile. A resist sidewall with insufficient verticality or excessive roughness will transfer these imperfections into the dielectric trench, creating metal fill voids or sidewall roughness that increases line resistance and degrades electromigration lifetime.

Metal Deposition and Barrier Formation

Following trench etch and resist/gap-fill strip, the MET4 module deposits a refractory metal diffusion barrier layer (typically Ta/TaN) to prevent copper ion migration into surrounding dielectrics and, critically in a BSI CIS, into the underlying pixel region where it could introduce dark current and defect-mediated noise. The barrier layer must conformally coat the trench sidewalls and via bottoms while maintaining sufficiently low contact resistance at the Metal 3 interface. Sputter-based physical vapor deposition (PVD) or atomic layer deposition (ALD) processes nucleate a thin, continuous film on all exposed surfaces. Any pinholes or discontinuities in this barrier create direct diffusion pathways for metal atoms into the dielectric stack.

Following barrier and Cu seed deposition, electrochemical deposition (ECD) fills both the Via-3 cavities and MET4 trenches simultaneously. In Cu dual-damascene processes, superchemdeposition growth nucleates at the via bottom and fills upward without seam or void formation, as any internal voids would increase resistance and create electromigration reliability vulnerabilities.

Planarization Physics

The CMP module executes sequential Cu CMP and barrier CMP steps to remove overburden material, leaving metal isolated within the trench recesses. The mechanism relies on the differential removal rates of metal versus dielectric under combined mechanical abrasion and chemical dissolution. In the 40nm BSI CMOS image sensor context, CMP must achieve global planarization across the wafer while avoiding dishing in wide metal features and erosion in dense regions—both of which would degrade the subsequent ILD4 surface planarity and propagate topography into upper levels. The chemical component of CMP involves oxidation of the metal surface followed by mechanical removal of the oxidized layer, with slurry chemistry tuned to maintain selectivity between metal and dielectric.

Interfaces and Failure Propagation

Upward Interfaces: MET4 to ILD4

The MET4 surface topography directly impacts the subsequent ILD4 deposition and upper metal patterning. If CMP produces excessive dishing in wide MET4 lines, the ILD4 deposition will fill the recess but create localized dielectric thinning that can cause inter-level dielectric breakdown or metal-to-metal short circuits at upper levels. Conversely, if CMP leaves slurry particles or metal residue, it can nucleate inter-level leakage paths that compromise sensor reliability.

Downward Interfaces: MET4 to Via-3 and Lower Metals

The MET4-to-Via-3 dual-damascene transition is a critical reliability node. Incomplete metal fill at the via bottom, or barrier layer delamination during CMP, creates high-resistance contacts that degrade signal integrity in the pixel readout chain. Since the BSI CMOS image sensor relies on correlated double sampling (CDS) to suppress reset noise, any resistance variation at MET4 via landings translates into pixel-to-pixel conversion gain non-uniformity. This non-uniformity is particularly damaging because it introduces fixed-pattern noise (FPN) that cannot be corrected by CDS alone and requires additional digital correction, increasing readout complexity.

Lateral Interfaces: Pixel Array vs. Peripheral Logic

The transition from the pixel array region to the peripheral logic region on MET4 involves a dramatic change in metal density and pattern geometry. The pixel array may use MET4 as a light-shielding or reflective grid with periodic openings aligned to pixel boundaries, while the peripheral logic uses MET4 for dense signal routing. This density transition creates CMP loading effects—where the array region experiences different removal rates than the logic region—and can induce metal height discontinuities at the boundary. These height discontinuities propagate upward through subsequent dielectric and metal layers, eventually affecting bonding pad planarity and wire bond reliability.

Failure Propagation Pathways

Metal diffusion through compromised barrier layers is a particularly insidious failure mode in BSI CIS. If metal ions migrate from MET4 through barrier defects into the underlying dielectric and ultimately reach the photodiode depletion region, they introduce deep-level traps that enhance generation-recombination current, manifesting as elevated dark current and random telegraph signal (RTS) noise in affected pixels. The high electric fields near the FD region amplify the impact of even small concentrations of metal contamination, making barrier integrity at MET4 a first-order reliability concern. The fundamental physics here involves trap-assisted carrier generation enhanced by the Poole-Frenkel effect, where the local electric field lowers the emission barrier for carriers trapped at deep-level defects, exponentially increasing the generation rate.

Electromagnetic crosstalk between MET4 signal lines and the pixel array is another failure pathway. In stacked sensor architectures where logic chips are bonded above the pixel array, MET4 can serve as a shielding plane to suppress electrical coupling between the logic and pixel domains—but only if the shielding metal is properly grounded and spatially separated from signal-carrying lines. Interposed layers can combine connection and shielding functions, where a grounded shielding portion is spatially isolated from the connecting portion to minimize parasitic capacitance. Failure to maintain this separation introduces parasitic capacitance that degrades signal-to-noise ratio (SNR) and can cause row-to-row signal corruption in the pixel readout.

Optical Interaction in BSI Architecture

The BSI architecture introduces a unique interface consideration for MET4 that is absent in conventional logic processes. Because the silicon substrate is thinned from the backside to allow light to reach the photodiodes from beneath, the frontside metal stack—including MET4—faces the photosensitive region. In this configuration, MET4 can function as an optical reflector that returns unabsorbed photons back into the silicon, effectively doubling the optical path length and improving QE, particularly for near-infrared (NIR) wavelengths that penetrate deeply into the silicon. The reflector effectiveness depends on the metal surface roughness after CMP, the metal composition, and the thickness of any overlying dielectric that forms the optical cavity.

However, this reflector function introduces a constraint: the MET4 pattern in the pixel array region must maintain optical uniformity to avoid pixel-to-pixel QE variation. Any CMP-induced roughness or metal height variation across the array translates directly into QE non-uniformity, which appears as optical fixed-pattern noise in the final image. This constraint is unique to image sensor BEOL and does not exist in logic or memory BEOL flows where metal optical properties are irrelevant.

Capacitive Coupling to Photosensitive Regions

MET4 lines running over the pixel array introduce parasitic capacitance to the underlying photodiode and FD nodes. This parasitic capacitance adds to the total FD capacitance, directly reducing conversion gain—the voltage change per electron of collected charge. In the 40nm BSI CMOS image sensor, where conversion gain is a critical performance metric, the MET4 routing density over the pixel array must be minimized or strategically placed over non-photosensitive regions such as the transfer gate and reset transistor areas. This creates a routing constraint that is unique to image sensor design and must be respected during MET4 layout planning.

Walk the Real Module

To explore the actual MET4 integration steps in detail, including the specific sequence of deposition, lithography, etch, and planarization operations, readers can Open METAL 4 TRENCH - Photo in the interactive flow. This interactive walkthrough provides step-by-step visibility into how the 40nm metal-four interconnect integration is executed in the actual process sequence, complementing the principle-level discussion presented here.

The interactive flow reveals how the MET4 module connects to the preceding Via-3 and ILD3 steps and how it feeds into subsequent ILD4, passivation, and bonding pad formation. Understanding this connectivity is essential for diagnosing yield issues that span multiple modules—for example, a MET4 trench depth variation traced to ILD3 thickness non-uniformity, or a via-3 open traced to MET4 CMP over-polish.

For those studying the broader 40nm BSI CMOS Image Sensor Process Flow: Integration Principles, Device Physics, and Module Dependencies, the interactive module serves as a bridge between the theoretical integration logic and the practical step-by-step execution. It reinforces how each physical mechanism discussed above maps to a specific process operation, and how the entry and exit states of the MET4 module constrain both upstream and downstream process windows.

Related Learning Paths

To build a complete understanding of the 40nm BSI CMOS image sensor interconnect integration, several adjacent topics merit exploration:

• The 40nm BSI CMOS Image Sensor Process Flow: Integration Principles, Device Physics, and Module Dependencies provides the overarching framework into which MET4 fits, explaining how front-end photodiode and transistor modules constrain BEOL design choices.

• The 40nm BSI CMOS Image Sensor Third Interlayer Dielectric Integration: Process Flow Principles and Device Physics covers the ILD3 module housing MET4 and Via-3, detailing how dielectric planarization quality directly affects MET4 lithographic performance.

• The 40nm BSI CMOS Image Sensor Via-Three Integration: Process Flow Principles and Device Physics examines the Via-3 module that creates the vertical cavities upon which MET4 lands, explaining the physics of via etch, barrier conformality, and dual-damascene fill.

Together, these three adjacent modules—ILD3, Via-3, and MET4—form a tightly coupled sub-sequence where process quality at each step constrains the performance envelope of the next. Mastering this sub-sequence is essential for any engineer working on 40nm BSI CIS BEOL integration.

Future Outlook

As BSI CMOS image sensors continue to scale pixel pitch and adopt three-dimensional stacking architectures, the MET4 module faces evolving challenges. The trend toward stacked pixel-logic chips, where the logic wafer is bonded face-to-face with the pixel wafer, redefines the role of upper metal levels. MET4 may transition from a purely routing and shielding layer to a bonding-interface layer that must simultaneously provide mechanical robustness for wafer-to-wafer bonding, electrical connectivity through hybrid bonding structures, and electromagnetic shielding.

The adoption of Cu-based interconnects in advanced CIS nodes introduces barrier layer scaling challenges. As trench dimensions shrink, the barrier layer occupies a larger fraction of the trench cross-section, increasing line resistance. Novel barrier materials and ALD techniques are being explored to achieve thinner, more conformal barriers that maintain diffusion blocking capability while reducing resistance.

In the optical domain, the growing interest in NIR sensitivity for automotive and security applications places new demands on MET4 as a reflector. NIR photons penetrate deeply into the silicon substrate, requiring the MET4 reflector geometry and the optical cavity thickness to be co-optimized with the backside thinning process. This co-optimization represents a shift from treating MET4 as a purely electrical interconnect to recognizing it as an opto-electrical structure whose geometry influences both signal routing efficiency and quantum efficiency.

Furthermore, the suppression of RTS noise and dark current in increasingly small pixels demands ever-stricter control of metal contamination from MET4 barriers. The electric field enhancement effects near the FD region, which amplify the impact of trace metal contaminants through field-assisted emission mechanisms, mean that barrier integrity requirements will tighten with each pixel generation. This drives innovations in barrier material science and CMP chemistry to minimize metal ion release and residue generation. The high-concentration surface doping profiles and steep gradients used to suppress UV-induced dark current at the photodiode surface are themselves sensitive to metal contamination, creating a compounding reliability challenge as pixel sizes shrink and electric fields intensify.