What is the 14nm FinFET semiconductor process flow?

The 14nm FinFET process flow is an advanced semiconductor manufacturing sequence that uses three-dimensional fin-shaped transistor structures instead of planar transistors. The fins provide better electrostatic control of the channel, significantly reducing short-channel effects and leakage current while enabling continued scaling beyond the limits of planar technology.

How does 14nm FinFET differ from 28nm planar technology?

The primary difference is the transistor architecture: 14nm uses 3D fin structures where the gate wraps around the channel on three sides, while 28nm uses traditional planar (flat) transistors. This tri-gate structure provides superior electrostatic control, enabling ~50% power reduction or ~20% performance improvement at the same power. The process flow also introduces new modules like fin patterning (SADP/SAQP), fin recess, and epitaxial source/drain wrapping around fins.

How many process steps are in the 14nm FinFET flow?

The 14nm FinFET process flow on SemiFlows contains 362 detailed process steps, spanning fin formation, gate patterning, source/drain engineering, contact metallization, and back-end-of-line interconnects.

What is SADP in 14nm FinFET manufacturing?

SADP (Self-Aligned Double Patterning) is a lithography technique used in 14nm FinFET manufacturing to create fin patterns at pitches below the resolution limit of single-exposure lithography. It involves depositing a conformal spacer film on mandrel structures, then removing the mandrels to leave spacer pairs that define the fin locations at half the mandrel pitch.

14nm FinFET - 14nm 工艺流程

本步在 PEALD Oxide Hardmask Deposition 后，随后为 CSOH Spin Coat 和 SC SOC Coat。等离子体产生的活性物种参与成膜，但电荷、离子作用和应力仍可能影响下层。沉积本身不完成自对准接触开口。

沉积与后续图形转移

沉积建立连续的含 Si–N 网络，后续光刻和刻蚀才把横向图形逐层转移。沉积本身不定义最终开口或线宽。成膜反应、表面供料和局部形貌影响覆盖；膜的组成、氢含量、密度及应力又会影响后续加工响应，不能从 SiN 名称推断唯一沉积方法或完全相同的膜质。

刻蚀选择性描述两种材料在特定条件下的相对去除速率。反应产物的挥发性、表面钝化、离子作用以及膜的实际组成共同决定它。Si–N 键较强并不意味着 SiN 在所有刻蚀条件下都比硅或氧化物耐蚀；硬掩膜自身的图形化也需要能够去除 SiN 的步骤。

14nm FinFET预览

工艺截面图

本步要点

原理展开

沉积与后续图形转移

保护能力与集成边界

风险与挑战

14nm FinFET预览

工艺截面图

本步要点

原理展开

沉积与后续图形转移

保护能力与集成边界

风险与挑战