STI filling, planarization and recess can serve different geometric goals. Filling places isolation material into a cavity. CMP establishes an intermediate surface. A later recess can deliberately lower isolation relative to adjacent semiconductor where that relative height is needed. Removing some material afterward does not mean the earlier fill was pointless.
Completion is defined by the next handoff
A filled trench solves an occupancy problem: the intended isolation region contains dielectric rather than an open space. It does not by itself establish every surface height needed by later device construction. A planarized surface is also an intermediate result, not necessarily the final exposure state of all active regions.
For a fin-based device example, a later sequence may need part of a semiconductor feature exposed above surrounding isolation. The required relative geometry differs from the earlier goal of filling the isolation region. The actual flow must establish when and how this happens; a planar transistor or an image-sensor isolation module should not automatically be assigned the same recess sequence.
Process checkpoint
Understand Fin Recess Etch in context
Observe how lowering STI oxide reveals more fin sidewall without lowering the silicon fin top.
Process context for “Why STI Can Be Recessed After Filling and CMP”: 14nm FinFET · FIN_RECESS · Step 66
Track material quantity and geometric role separately
| Operation | Question it answers | Question still open |
|---|---|---|
| Fill | Is the intended cavity occupied? | What is the final exposed height? |
| Planarization | Is the intermediate surface suitable for the next operation? | Which regions must later be exposed? |
| Selective recess, where used | Has the intended relative isolation level been established? | Are the remaining interfaces and isolation continuous? |
An isolation feature can remain functional even when its upper boundary moves. Conversely, the presence of some dielectric does not prove that the remaining geometry provides adequate isolation.
Intended recess is not accidental material loss
Two cross-sections can show similar lowered dielectric surfaces but represent different stories. One may be a designed recess after a controlled intermediate state. The other may reflect unintended loss during an earlier operation. The distinction comes from the specified process objective and sequence, not merely the final outline.
That is why a general label such as “etchback” is insufficient. The reader should identify the material targeted for removal, the boundary that should remain, and the adjacent material that should be preserved. Selectivity and interface condition belong to this handoff, even when the drawing only shows a change in height.
A reading exercise: what has become accessible?
Compare an intermediate isolation surface with a later recessed state. Rather than immediately asking how much material disappeared, ask what surface of the adjacent semiconductor became accessible. Then ask what subsequent structure can use that exposed surface.
This links the material removal to a device function. It also prevents a common overstatement: a taller exposed shape in a teaching diagram is not a measured improvement in drive current. Electrical consequences depend on the complete geometry, gate control, interfaces and operating conditions.
Source links
References
Silicon VLSI Technology - Full
James D. Plummer, Michael D. Deal, Peter B. Griffin
Silicon VLSI Technology · ISBN 978-0130850379