14nm Fin Trench Etch and Fin Recess Integration

What This Module Actually Changes

The fin recess integration module sits after isolation formation and before the gate module in the linked 14nm FinFET flow. Its first operation, Fin Trench Etch, acts on exposed silicon. Subsequent fin-profile adjustment and surface preparation complete the transition into gate formation. This placement matters: the module is not simply another name for lowering the surrounding shallow trench isolation oxide.

Three operations are easily confused in explanations of FinFET processing. Silicon trench etching removes semiconductor material to define or refine a silicon profile. Silicon fin recess removes material from the fin itself. Isolation oxide recess lowers dielectric around a fin and can expose more of the existing silicon sidewall. These operations affect different materials and can change the exposed geometry in different directions. Identifying the removed material is therefore the starting point for understanding the module.

The node label does not specify a universal integration sequence. The ordering discussed here belongs to the linked educational flow. Other FinFET implementations may distribute silicon patterning, isolation fill, dielectric recess, and surface conditioning differently. A useful explanation preserves this distinction instead of treating one sequence as a requirement for every process bearing the same node name.

Sequence and Interfaces

In this flow, isolation and its notch-related module are upstream of the fin recess module. The silicon trench operation discussed here consequently occurs after those isolation operations. It must not be relocated to the initial pre-fill fin patterning stage merely because both stages contain a silicon etch. Similar operation names do not establish that two process positions have the same starting surface or purpose.

Within the fin recess module, trench-profile formation precedes further fin-profile adjustment and surface preparation. The gate module then consumes the resulting semiconductor and dielectric topography. This ordering establishes the relevant interfaces: incoming isolation geometry constrains which surfaces are accessible, while the outgoing fin geometry constrains the surfaces that subsequent gate layers must cover.

This is also distinct from a later source/drain recess beside an already patterned gate. A source/drain recess prepares a local region for subsequent junction or epitaxial integration. Its placement, mask environment, and purpose differ from the pre-gate module discussed here. Transferring the explanation of one operation to another solely because both are called recess would erase the integration context that makes each operation understandable.

Silicon Removal and Profile Control

Plasma-assisted silicon etching combines surface chemistry with energy delivered by charged particles. Reactive neutral species can reach exposed surfaces from many directions and participate in reactions that form removable products. Positive ions accelerated across the sheath arrive preferentially toward the wafer and can activate reactions or remove inhibiting material at surfaces they strike. The resulting profile reflects the interaction of those mechanisms, rather than directionality being a property of neutral radicals alone.

The lateral protection of a fin and the removal occurring at an exposed horizontal region need to remain compatible. If sidewall protection is insufficient, lateral silicon loss can narrow the fin or change its taper. If protection persists where removal is intended, the profile can become incomplete or nonuniform. Ion-related damage and residue formation are additional concerns: an apparently acceptable outline does not prove that the surface is ready to become an electrically important interface.

Etch selectivity is the ratio between the etch rates of different materials in a process [T1]. This definition describes relative removal, not an absolute guarantee that a neighboring material remains unchanged. In the module considered here, preserving surrounding dielectric while removing the intended silicon requires attention to both that relative response and the incoming geometry. An idealized perfectly selective boundary should not be substituted for the finite selectivity of a real material interaction.

Profile control also depends on access. Dense and sparse features can experience different transport and local reaction conditions. A top-down view can therefore conceal differences in depth, taper, or sidewall condition. The physical issue is whether reactants, ions, and reaction products can reach or leave the relevant surfaces consistently, not simply whether every opening had the same drawn outline.

Geometry and Device Consequences

A FinFET gate couples to several surfaces of the semiconductor body. Changing the fin cross-section consequently changes both the conducting perimeter available to the gate and the distribution of electrostatic control. Fin height and fin width are different variables: increasing the gated perimeter can increase current capability, while the ability to control the body also depends on width, gate length, dielectric coupling, junctions, and the underlying semiconductor region.

For that reason, neither a taller fin nor a deeper recess universally improves leakage. Removing silicon from the fin top can reduce its height; lowering surrounding oxide can expose more sidewall without making the silicon body taller. Their electrical effects cannot be inferred from the word recess alone. A claim about current or leakage must identify which geometry changed and which other conditions are being held comparable.

Surface quality adds another dependency. Roughness, defects, or chemical residue can alter the interface presented to subsequent gate formation. Local geometry and surface condition can contribute to field nonuniformity, interface trapping, and device variability. These are directional risks rather than an inevitable failure for every irregularity; their impact depends on severity, position, and later processing.

Failure Propagation and Useful Distinctions

Unintended lateral silicon removal tends to reduce the remaining fin width rather than broaden it. Unwanted dielectric removal instead changes the environment around the fin and may expose additional semiconductor. Confusing these directions leads to incorrect explanations of both dimensional variation and electrical consequences. The affected material and the location of removal should remain explicit throughout a causal argument.

An incomplete or nonuniform trench profile can pass an uneven geometry into the following fin adjustment. Later surface preparation may remove reaction products or condition exposed surfaces, but it cannot be assumed to restore semiconductor that was already removed. Similarly, a subsequent conformal layer follows the available geometry; conformality does not by itself correct an unintended fin shape.

Selectivity, surface condition, and dimensional consistency must therefore be considered together. Improving one property does not automatically improve all the others. A removal mechanism that preserves one neighboring material may still leave residue, while more energetic surface activation can change both removal behavior and damage. These interactions explain why the module is best understood as a sequence of coupled material transformations rather than a single ideal etch event.

Connecting the Explanation to the Flow

The Fin Trench Etch entry in the interactive flow provides the specific context for this article. The fin recess explanation discusses the neighboring profile-adjustment subject, and the gate integration article explains a downstream consumer of the prepared surface.

When comparing those pages, follow three questions: what material is removed, what geometry remains, and which subsequent operation uses it? Those questions preserve the difference between silicon trench formation, fin adjustment, and dielectric recess. They also make clear why evidence for a general etching mechanism does not establish a universal node-specific recipe or manufacturing sequence.