14nm FinFET Shallow Trench Isolation Notch Integration: Process Flow Principles and Mechanism Deep Dive

Role in the Complete Flow

In the 14nm FinFET technology node, the shallow trench isolation (STI) notch module occupies a uniquely critical position within the broader 14nm FinFET process flow [T1]. The STI structure itself serves as the fundamental isolation scheme between adjacent active devices, replacing the older localized oxidation of silicon (LOCOS) approach by etching trenches into the silicon substrate and refilling them with dielectric material [T1]. The notch feature is an additional geometric refinement — a deliberate lateral recess carved into the upper portion of the STI dielectric — that creates a stepped profile at the fin–isolation boundary [A1].

The upstream handoff to this module comes from the base STI formation sequence, which includes pad oxide growth, silicon nitride hard mask deposition, trench etching, liner oxidation, and high-density plasma chemical vapor deposition (HDP-CVD) oxide fill [P2]. After chemical mechanical polishing (CMP) planarizes the fill oxide to the nitride stop layer, the STI_NOTCH module receives a structure where the oxide surface is approximately coplanar with the hard mask, and the fins are defined but still embedded within the dielectric matrix [P2].

Downstream, the notch module must deliver a precisely shaped recess in the STI oxide such that the fin tops protrude above the recessed isolation surface [A1]. This protrusion is essential because the fin sidewalls and top surface serve as the channel region of the FinFET, and subsequent gate stack deposition must wrap continuously around the exposed fin [T2]. If the notch is absent or insufficient, the gate cannot fully surround the upper fin region, degrading electrostatic control and increasing subthreshold leakage [T2]. Thus, the STI_NOTCH module acts as the geometric bridge between isolation formation and active device definition [T1].

Entry State and Sequence Logic

Upstream Dependencies

The STI_NOTCH module enters the process flow after a series of structurally defining steps have already been completed (Engineering Practice). The 14nm FinFET shallow trench isolation process flow delivers a planarized substrate where silicon nitride hard mask material remains over active fin regions, and HDP-CVD oxide fills the trenches between them [P2]. The entry state is therefore a composite stack: silicon substrate with etched fin structures, a pad oxide layer, a silicon nitride hard mask, and fill oxide that has been polished back [A1].

A critical upstream dependency is the STI3 SiN Hard Mask Deposition step, which deposits a plasma-enhanced chemical vapor deposition (PECVD) silicon nitride layer used as a selective etch mask for the notch recess [A1]. The STI3 SiN hard mask serves a different purpose than the original nitride CMP stop layer: it defines where the notch etch will occur (over isolation regions) while protecting active fin regions from lateral etch attack [A1]. The STI3 SiN Hard Mask Deposition integration principles rest on the need for conformal coverage over the existing topography, sufficient etch selectivity to the underlying oxide, and controlled stress to avoid inducing defects in the already-formed fin structures [A1].

Sequence Positioning and Logic

The notch module is positioned after STI CMP but before fin reveal and gate stack formation [T3]. This placement is deliberate: if the notch were created before CMP, the planarization process would remove or distort the recessed profile; if it were created after gate formation, the gate stack would be damaged by the notch etch chemistry [P2]. The sequence logic therefore follows a "define → fill → planarize → selectively recess" pattern, where each step preserves the structural integrity established by the previous one (Engineering Practice).

The STI_NOTCH module process flow for 14nm FinFET typically involves several sub-steps: deposition of the STI3 SiN hard mask, patterning to open isolation regions, anisotropic oxide etch to create the notch recess, and subsequent removal of the STI3 SiN hard mask [T3]. Each sub-step has strict selectivity requirements — the oxide etch must stop on or near the silicon fin surface without consuming the fin material itself [P1].

Physical and Chemical Mechanisms

PECVD Silicon Nitride Deposition

The STI3 SiN hard mask is deposited by plasma-enhanced chemical vapor deposition (PECVD), which uses a plasma discharge to dissociate precursor gases and drive film formation at relatively low substrate temperatures [T3]. The fundamental mechanism involves electron-impact ionization and dissociation of precursor molecules in the gas phase, generating reactive radicals that adsorb onto the wafer surface and undergo surface reactions to form a solid silicon nitride film [P1].

The PECVD silicon nitride film quality depends on the balance between radical flux, ion bombardment energy, and surface temperature [P1]. Higher ion energies improve film density and step coverage but can introduce stress and damage to underlying layers [P3]. Lower energies yield softer films with higher hydrogen content, which may compromise etch selectivity [P1]. The integration tradeoff is between conformality (needed to cover the existing topography uniformly), film density (needed for etch resistance), and stress (which must be managed to avoid fin deformation or defect generation in the silicon substrate) [A1].

Notch Etch Chemistry

The notch recess is created by a selective oxide etch process, typically using fluorocarbon-based plasma chemistry [P1]. The mechanism of plasma etching involves synergistic interaction between energetic ions and reactive neutral radicals at the oxide surface [P1]. Fluorocarbon radicals (such as CF, CF₂) adsorb onto the SiO₂ surface and react to form volatile silicon fluoride products (SiF₄) and carbon-oxygen byproducts, while ion bombardment provides directional kinetic energy that breaks surface bonds and enhances the etch reaction rate [P1].

The etch selectivity to silicon nitride is critical: the STI3 SiN hard mask must resist the oxide etch chemistry so that only the exposed isolation oxide is removed [P1]. Fluorocarbon chemistries naturally form a fluorocarbon polymer layer on non-oxide surfaces, which acts as a passivation film that protects silicon nitride from etching while the oxide beneath is consumed [P1]. This polymer-driven selectivity mechanism is the fundamental reason the notch can be formed with lateral precision [A1].

The notch profile is governed by the balance between chemical etching (isotropic, driven by radical flux) and physical sputtering (anisotropic, driven by ion energy) [P1]. A slightly tapered notch sidewall is often desirable to facilitate subsequent conformal deposition of gate materials, while a flat notch bottom ensures uniform fin height across the device array [T1].

SiN Hard Mask Removal

After the notch is formed, the STI3 SiN hard mask must be removed without damaging the exposed oxide notch or the fin surfaces [A1]. This is typically achieved using a phosphoric acid-based wet etch or a selective plasma etch that consumes silicon nitride at a much higher rate than SiO₂ or silicon [P1]. The removal mechanism relies on the chemical difference between Si₃N₄ and SiO₂: phosphoric acid hydrolyzes Si-N bonds but is relatively inert to Si-O bonds, providing the necessary selectivity (Engineering Practice).

Interfaces and Failure Propagation

Upward-Propagating Tradeoffs

The STI_NOTCH module is sensitive to upstream variations in multiple ways (Engineering Practice). If the preceding STI CMP step exhibits pattern-dependent dishing or erosion — where the oxide removal rate varies with local pattern density — the entry surface height will be non-uniform across the wafer [P2]. This means the notch etch starts from an inconsistent baseline, leading to fin height variation across the die [A1]. Since FinFET drive current is directly proportional to the effective channel width, which depends on fin height [T2], this variation propagates into device performance spread.

Similarly, if the HDP-CVD oxide fill has voids or seams from incomplete trench filling, the notch etch can open these internal defects, creating catastrophic leakage paths between adjacent devices [T1].

Downward Consequences

The notch depth directly controls the effective fin height that will be available for channel formation (Engineering Practice). An excessively deep notch exposes too much fin height, increasing drive current but also increasing parasitic capacitance and potentially degrading short-channel control [T2]. An insufficiently deep notch leaves the fin partially buried, reducing the effective channel width and lowering drive current [T2].

The notch sidewall angle affects the conformality of subsequent gate dielectric and metal gate deposition [T3]. A vertical notch sidewall may create coverage gaps at the corner where the fin meets the isolation; a gently sloped sidewall allows better step coverage but consumes more lateral space, reducing device density [T1].

Lateral etch of the notch — where the oxide recess extends horizontally beneath the STI3 SiN hard mask — is a key failure mode [A1]. If the hard mask adhesion is poor or the etch chemistry lacks sufficient anisotropy, the notch can undercut the active region, creating a weakened structure that may collapse during subsequent processing or create uncontrolled gate overlap [P1].

Stress and Defect Interfaces

The PECVD silicon nitride hard mask introduces tensile or compressive stress depending on deposition conditions [A1]. This stress is transferred to the underlying silicon fins, and at 14nm dimensions, even modest stress can generate dislocations or alter carrier mobility through piezoresistive effects [T3]. The notch etch itself can create plasma-induced damage on exposed fin surfaces, introducing surface states that increase interface trap density and degrade subthreshold swing [P1].

Walk the Real Module

To see how these principles translate into a concrete process sequence, you can Open STI_NOTCH Step 53 in the interactive flow (Engineering Practice). This interactive module walk-through shows the exact placement of the notch formation step within the 14nm FinFET process architecture, illustrating how the STI3 SiN hard mask deposition, patterning, oxide recess etch, and mask removal are sequenced relative to the upstream STI fill/planarization and the downstream fin reveal and gate formation steps [T3].

The interactive flow also highlights the relationship between the notch module and the subsequent fin recess integration steps, which further shape the fin geometry for epitaxial source/drain growth [A1]. Understanding this sequence is essential because the notch profile established here directly constrains the fin geometry available for all downstream modules [A1].

Related Learning Paths

For engineers seeking to build a complete understanding of the 14nm FinFET isolation and fin formation architecture, several adjacent topics are worth exploring:

• The foundational 14nm FinFET shallow trench isolation process flow covers the upstream trench etch, oxide fill, and CMP planarization steps that create the entry state for the notch module [T1].
• The broader 14nm FinFET process flow provides the end-to-end integration context, showing how the notch module fits within the complete device fabrication sequence from substrate preparation through metal interconnects [T3].
• The fin recess integration process flow describes the downstream module that further shapes fin geometry after the notch is formed, preparing the structure for selective epitaxial source/drain growth [A1].

Each of these modules shares common integration challenges — stress management, etch selectivity, profile control, and pattern-dependent uniformity — and understanding the interfaces between them is essential for diagnosing yield-limiting issues in 14nm FinFET manufacturing [T3].

Future Outlook

As FinFET scaling continues toward 7nm and beyond, the STI notch concept is evolving into more complex isolation architectures [T2]. Gate-all-around (GAA) nanosheet and nanowire devices require even more precise control of the isolation-to-channel interface, and the notch geometry must accommodate multiple vertically stacked channels [T2]. The transition from PECVD silicon nitride hard masks to atomic layer deposition (ALD) hard mask materials is being explored to achieve better conformality and etch selectivity at these advanced dimensions [P1].

Additionally, the drive toward lower thermal budgets — motivated by the need to preserve ultra-shallow junction profiles and strained-channel enhancements [P3] — is pushing the industry toward plasma-enhanced and remote-plasma processes that can achieve notch formation at lower temperatures. The fundamental tradeoffs between anisotropy, selectivity, and damage that govern the 14nm STI notch module will remain central to these future developments, even as the specific materials and geometries evolve [T3].