14nm FinFET Shallow Trench Isolation Notch Integration: Process Flow Principles and Mechanism Deep Dive

Role in the Complete Flow

In the 14nm FinFET technology node, the shallow trench isolation (STI) notch module occupies a uniquely critical position within the broader 14nm FinFET process flow. Shallow trench isolation physically etches trenches into the silicon substrate between active components and refills them with oxide dielectric to establish isolation [T1]. The notch feature is an additional geometric refinement — a deliberate lateral and vertical recess carved into the upper portion of the STI dielectric — that creates a stepped profile at the fin–isolation boundary.

The upstream handoff to this module comes from the base STI formation sequence, which includes pad oxide growth, silicon nitride hard mask deposition, trench etching, liner oxidation, and high-density plasma chemical vapor deposition (HDP-CVD) or spin-on dielectric fill. Thermal liner oxidation at high temperature provides corner-rounding at sharp trench edges to reduce stress and parasitic electrical effects [P2]. A thin silicon nitride stop layer deposited over a thin pad oxide layer serves as an integral polish stop during shallow trench isolation planarization . After chemical mechanical polishing (CMP) planarizes the fill oxide to the nitride stop layer, the STI_NOTCH module receives a structure where the oxide surface is approximately coplanar with the hard mask, and the fins are defined but still embedded within the dielectric matrix.

Downstream, the notch module must deliver a precisely shaped recess in the STI oxide such that the fin tops protrude above the recessed isolation surface. This protrusion is essential because the fin sidewalls and top surface serve as the channel region of the FinFET, and subsequent gate stack deposition must wrap continuously around the exposed fin. If the notch is absent or insufficient, the gate cannot fully surround the upper fin region, degrading electrostatic control and increasing subthreshold leakage. Thus, the STI_NOTCH module acts as the geometric bridge between isolation formation and active device definition.

Entry State and Sequence Logic

Upstream Dependencies

The STI_NOTCH module enters the process flow after base isolation trench etching and planarization have been completed. The 14nm FinFET shallow trench isolation process flow delivers a planarized substrate where silicon nitride hard mask material remains over active fin regions, and dielectric oxide fills the trenches between them. The entry state is therefore a composite stack: a silicon substrate with etched fin structures, a pad oxide layer, a silicon nitride hard mask, and fill oxide that has been polished back.

A critical upstream dependency is the STI3 SiN Hard Mask Deposition step, which deposits a silicon nitride layer used as a selective mask for the notch recess. The STI3 SiN hard mask serves a different purpose than the original nitride CMP stop layer: it defines where the notch etch will occur over isolation regions while protecting active fin regions from lateral etch attack. The STI3 SiN hard mask deposition integration principles rest on the need for conformal coverage over the existing topography, sufficient etch selectivity relative to the underlying oxide, and controlled film stress to avoid inducing defects in the fin structures.

Sequence Positioning and Integration Logic

The notch module is positioned after STI CMP planarization but before final fin reveal and gate stack formation. This placement is deliberate: if the notch recess were created before CMP, the planarization process would distort or erase the recessed dielectric profile; if performed after gate formation, the aggressive oxide etch chemistry would destroy the gate dielectric and work-function metals. The integration sequence therefore follows a "define -> fill -> planarize -> selectively recess" progression.

Following initial planarization, the module begins with the redeposition of an STI3 SiN hard mask layer over the STI oxide and active fin areas. An anti-reflective layer is deposited over the hard mask stack, followed by organic planarization and photoresist coating to support high-resolution lithographic patterning of the notch regions over the isolation dielectric. Plasma etching transfers the pattern through the anti-reflective layer, after which the resist stack is removed and plasma cleaning strips residual polymers. The exposed hard mask is selectively etched to open access windows down to the STI oxide surface. Following residue cleaning and dielectric liner passivation, chemical mechanical polishing and wet deglaze cleans prepare the exposed oxide recess area. Finally, selective wet or isotropic dry processing removes the sacrificial silicon nitride mask, leaving clean, protruded fin tops ready for downstream gate integration.

Physical and Chemical Mechanisms

PECVD Silicon Nitride Deposition

The STI3 SiN hard mask is typically deposited by plasma-enhanced chemical vapor deposition (PECVD), which uses a radio-frequency plasma discharge to dissociate silane (SiH4) and ammonia (NH3) or nitrogen (N2) precursors at lower temperatures than thermal nitridation. The fundamental mechanism involves electron-impact ionization and dissociation of precursor molecules in the gas phase, generating reactive radicals that adsorb onto the wafer surface and undergo surface condensation to form a solid silicon nitride film.

The PECVD silicon nitride film quality depends on the balance between radical flux, ion bombardment energy, and surface temperature. Higher ion energies improve film density and step coverage but can introduce stress and damage to underlying layers. Lower energies yield softer films with higher hydrogen content, which may compromise etch selectivity. The integration tradeoff is between conformality (needed to cover topography uniformly), film density (needed for etch resistance), and film stress (which must be managed to avoid fin deformation or defect generation in the silicon substrate).

Notch Etch Chemistry and Selectivity

The notch recess is created by a selective oxide etch process, typically using fluorocarbon-based plasma chemistry (such as CF4, C4F8, or CHF3 combined with Ar and O2). The mechanism of plasma etching involves synergistic interaction between energetic ions and reactive neutral radicals at the oxide surface. Fluorocarbon radicals (CF, CF2) adsorb onto the SiO2 surface and react to form volatile silicon fluoride products (SiF4) and carbon-oxygen byproducts (CO, CO2), while ion bombardment provides directional kinetic energy that breaks surface bonds and enhances the etch reaction rate.

The etch selectivity to silicon nitride is governed by fluorocarbon polymer deposition dynamics. On non-oxide surfaces such as Si3N4, oxygen is not liberated during etching to consume carbon, resulting in the steady-state accumulation of a thin fluorocarbon polymer passivation layer. This polymer layer inhibits radical adsorption and shields the nitride mask from sputtering, while on SiO2 surfaces, the intrinsic oxygen content consumes the carbon species as CO/CO2, allowing etching to proceed rapidly. This polymer-driven selectivity mechanism enables controlled lateral and vertical oxide recessing.

SiN Hard Mask Removal

After the notch is formed, the STI3 SiN hard mask must be removed without damaging the exposed oxide notch or the fin surfaces. This is typically achieved using a hot phosphoric acid (H3PO4) wet etch or a specialized isotropic dry etch. The wet removal mechanism relies on the chemical reaction between phosphoric acid and Si3N4, where hydronium ions hydrolyze Si-N bonds to form soluble silicic acid species and ammonium compounds, while Si-O bonds in the oxide remain significantly less reactive, providing high wet-etch selectivity.

Interfaces and Failure Propagation

Upward-Propagating Tradeoffs

The STI_NOTCH module is sensitive to upstream variations. Pattern-dependent dishing and nitride erosion during CMP can cause non-uniform remaining field oxide thickness across the die. This means the notch etch starts from an inconsistent baseline, leading to fin height variation across the wafer. Because FinFET drive current is directly proportional to the effective channel width (which depends on exposed fin height), this variation propagates into device threshold voltage and drive current spread.

Similarly, if the STI oxide fill contains internal seams or micro-voids from incomplete trench filling, the notch etch can open these internal defects, creating deep crevices that trap gate metal and form catastrophic electrical leakage paths between adjacent fins.

Downward Consequences

The notch depth directly controls the effective fin height that will be exposed for channel formation. An excessively deep notch exposes too much fin height, increasing drive current but also increasing parasitic source/drain-to-substrate capacitance and potentially degrading short-channel control. An insufficiently deep notch leaves the fin partially buried, reducing the effective channel width and lowering drive current.

The notch sidewall profile affects the conformality of subsequent gate dielectric and metal gate deposition. A vertical or undercut notch sidewall can create coverage voids at the corner where the fin meets the isolation; a gently sloped sidewall allows better step coverage but consumes more lateral space, reducing active area packing density.

Stress and Surface Damage Interfaces

The PECVD silicon nitride hard mask introduces mechanical stress depending on deposition parameters. This stress is transferred to the underlying silicon fins; at 14nm dimensions, even modest stress can generate crystal dislocations or alter local carrier mobility through piezoresistive effects. Furthermore, the notch plasma etch can induce surface damage on exposed fin sidewalls, creating dangling bonds and surface states that increase interface trap density (Dit) and degrade subthreshold swing.

Walk the Real Module

To see how these principles translate into a concrete process sequence, you can Open STI_NOTCH Step 53 in the interactive flow. This interactive module walk-through shows the exact placement of the notch formation sequence within the 14nm FinFET process architecture, illustrating how the STI3 SiN hard mask deposition, patterning, oxide recess etch, and mask removal are sequenced relative to upstream STI CMP and downstream fin reveal.

The interactive flow also highlights the relationship between the notch module and the subsequent fin recess integration steps, which further shape the fin geometry for epitaxial source/drain growth. Understanding this sequence is essential because the notch profile established here directly constrains the fin geometry available for all downstream modules.

Related Learning Paths

For engineers seeking to build a complete understanding of the 14nm FinFET isolation and fin formation architecture, several adjacent topics are worth exploring:

• The foundational 14nm FinFET shallow trench isolation process flow covers the upstream trench etch, oxide fill, and CMP planarization steps that create the entry state for the notch module.
• The broader 14nm FinFET process flow provides the end-to-end integration context, showing how the notch module fits within the complete device fabrication sequence from substrate preparation through metal interconnects.
• The fin recess integration process flow describes the downstream module that further shapes fin geometry after the notch is formed, preparing the structure for selective epitaxial source/drain growth.

Each of these modules shares common integration challenges — stress management, etch selectivity, profile control, and pattern-dependent uniformity — and understanding the interfaces between them is essential for diagnosing yield-limiting issues in 14nm FinFET manufacturing.

Future Outlook

As FinFET scaling continues toward 7nm and gate-all-around (GAA) nanosheet architectures, the STI notch concept evolves into multi-step channel release and isolation control schemes. Gate-all-around devices require even more precise control of the isolation-to-channel interface to accommodate multiple vertically stacked nanosheets.

Additionally, the transition from PECVD silicon nitride hard masks to atomic layer deposition (ALD) hard mask materials is widely adopted to achieve extreme conformality and atomic-scale selectivity. Furthermore, lower thermal budget requirements — driven by the need to preserve ultra-shallow junctions and strain engineering — continue to push the industry toward remote-plasma chemical etches that achieve isotropic recessing with minimal sub-surface damage.