14nm Fin Recess Integration: Mechanisms, Physics, and Process Control

Function in the Complete Flow

In advanced multi-gate architectures, the transition from planar field-effect transistors to three-dimensional structures represents a fundamental shift in electrostatic control and channel design. Non-planar three-dimensional devices with multiple gates are more promising candidate for high current drive capability and better short-channel characteristics [P1]. Within a 14nm fin field-effect transistor (FinFET) manufacturing sequence, the silicon fin structure is initially formed with an overgrown vertical profile following high-aspect-ratio trench etching. The 14nm fin recess integration step serves as a decisive physical tuning module where this raw etched silicon fin profile is locally redefined prior to gate dielectric and gate electrode formation.

The primary functional objective of the 14nm fin recess integration step is to anisotropically remove silicon from the fin top, intentionally recessing the fin relative to the surrounding oxide to decouple lithographically defined fin height from the electrostatically active channel height. In FinFET device physics at the 14nm regime, short-channel behavior and electrostatic channel control are governed primarily by the vertical fin sidewalls wrapped by the gate stack, rather than by conduction across the fin top. Recessing the fin top establishes a controlled silicon geometry that minimizes parasitic top-corner conduction and prepares a well-defined surface for subsequent sacrificial oxide recess and selective thick gate oxidation steps.

Positioned directly after primary fin trench etching and hard mask removal, this silicon recess operation hands off a structurally optimized three-dimensional fin profile. It establishes the geometric baseline for all downstream front-end-of-line (FEOL) operations, including channel strain engineering, punch-through stopper (PTS) well implantation, sacrificial gate deposition, and eventual replacement metal gate (RMG) formation.

Upstream Input State

Prior to entering the fin recess etch module, the wafer undergoes aggressive top-down lithography and silicon deep trench etching. The input state inherited by this step exhibits distinct structural, material, and surface topographic characteristics:

• As-Etched Silicon Fin Topography: The silicon fins stand as high-aspect-ratio vertical walls separated by open trenches. Their total physical height reflects the deep silicon trench etch depth combined with remaining hard mask height.
• Patterned Fin Profile and Line-Width Roughness: The incoming silicon fins have been defined using sub-diffraction multi-patterning techniques such as self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP). Consequently, the fins inherit upstream line-width roughness (LWR), minor pitch-walking variations, and slightly tapered vertical sidewall angles from reactive ion etching.
• Hard Mask Stripped Surface: The primary silicon nitride or oxide hard mask caps used to pattern the deep fin trenches have been cleared, leaving bare single-crystal silicon exposed at the fin tops and upper sidewalls.
• Sub-Surface Damage and Strain: High-energy mechanical forces and energetic ion bombardment from prior reactive ion etching leave micro-strain and localized lattice displacement damage along the exposed silicon surfaces. Managing ion bombardment energy during reactive ion etching is critical because PID is well known to degrade both gate dielectric and metal-oxide-semiconductor field-effect transistors (MOSFETs) reliability .

Managing these incoming surface and material conditions is essential because any spatial non-uniformity in hard mask removal or surface damage directly perturbs the etch front during the fin recess etch mechanism.

Physical and Chemical Mechanisms

The core mechanism of the Fin recess etch relies on achieving highly directional, anisotropic silicon material removal from the fin top while protecting the vertical fin sidewalls to maintain strict critical dimension (CD) control. In dry etching modules, directional or anisotropic etching is possible with plasma etch systems [T1]. This operation typically leverages an inductively coupled plasma (ICP) reactive ion etch scheme tuned for halogen-based silicon removal.

Anisotropic Silicon Removal and Surface Reactions

In a halogen-based silicon recess approach, precursor gases such as chlorine (Cl2), hydrogen bromide (HBr), or fluorine-containing chemistries are ionized in the plasma chamber to generate active halogen radicals and positive ions. These reactive radicals adsorb onto the exposed silicon fin tops, breaking covalent Si-Si bonds and forming volatile reaction products such as silicon tetrachloride (SiCl4) or silicon tetrabromide (SiBr4), which are evacuated continuously from the chamber.

To maintain anisotropy, directional ion bombardment supplied by RF substrate biasing accelerates positive ions normal to the wafer surface. These impinging ions transfer kinetic energy directly to the horizontal fin tops, accelerating chemical desorption and reaction rates normal to the surface.

Sidewall Passivation and Profile Integrity

To suppress lateral attack on the vertical fin sidewalls, passivating gas species (such as small additions of O2, N2, or fluorocarbon modifiers) are introduced into the plasma. These additives react with silicon and halogen radicals to form an ultra-thin protective passivation layer (such as silicon oxyhalide, SiOxFy or SiOxCly) on the fin surfaces.

Because horizontal fin tops experience direct, energetic ion bombardment, the passivation film on the top surface is continuously sputtered away, allowing rapid vertical silicon etching. In contrast, the vertical fin sidewalls receive negligible direct ion impact; the passivating film remains intact on the sidewalls, kinetics-suppressing lateral silicon removal and preserving fin width and sidewall slope.

Incoming Fin Profile           Directional Ion-Assisted Etch          Recessed Fin Geometry
     +-------+                          |  |  |  |                         +-------+
     |  Si   |                          V  V  V  V                         |       |  Recessed
     |  Fin  |                  +-----------------------+                  |  Si   |  Fin Top
     |       |                  |  Vertical Ion Impact  |                  |  Fin  |
+----+-------+----+             +----+-------+----------+             +----+-------+----+
|  Substrate/STI  |                  |  Si   |                        |  Substrate/STI  |
+-----------------+                  +-------+                        +-----------------+

Depth Uniformity and Aspect-Ratio Dependent Etching

The final vertical location of the recessed fin top dictates the initial height baseline for all subsequent gate dielectric and oxidation modules. Achieving sub-nanometer cross-wafer recess depth uniformity requires precise management of plasma density, gas distribution, and aspect-ratio dependent etching (ARDE). In dense fin arrays, localized radical depletion or ion shadowing can reduce the silicon etch rate relative to isolated regions. Modern tools utilize low-pressure, high-density ICP configurations operating in diffusion-dominated regimes to minimize micro-loading and maintain identical fin height across diverse layout densities.

Downstream Impact and Failure Propagation

The 14nm fin recess integration step acts as a critical watershed moment in FEOL processing. Because fin profile geometry governs how downstream oxidation and gate dielectric growth occur, variations in fin recess depth directly propagate structural and electrical failure modes into downstream modules.

Decoupling Electrostatic Control from Lithographic Height

By setting the top fin elevation prior to gate oxide growth, the module ensures that the active channel height (H_fin) is governed by uniform sidewall exposure rather than lithographic top-height variations. The relationship between silicon recess depth and electrical performance involves several key trade-offs:

• Under-Recessing (Insufficient Silicon Removal): Leaves the fin top excessively high relative to the isolation baseline. During subsequent oxidation, the tall fin top can suffer from non-uniform oxide growth and localized field crowding at the upper corners, causing threshold voltage (V_t) instability and increased parasitic corner leakage.
• Over-Recessing (Excessive Silicon Removal): Over-recessing removes too much silicon, shortening the final exposed fin height. This shrinks the total active channel area (W_eff = 2 * H_fin + W_fin), directly depressing the ON-state drive current (I_on) and transconductance (g_m) below target specifications.
• Passivation Breakdown and Sidewall Erosion: If sidewall passivation breaks down during the silicon recess etch, lateral etching degrades the fin sidewalls, reducing fin width (W_fin). Narrowing or tapering the fin degrades short-channel control and drives up drain-induced barrier lowering (DIBL) and subthreshold leakage (I_off).

Interface Integrity and Gate Dielectric Reliability

Non-uniform silicon recessing or aggressive ion damage at the fin top can create surface micro-roughness or sharp corner facets. When the sacrificial gate oxide and subsequent high-k gate dielectric (such as HfO2) are deposited, sharp fin top corners induce severe electric field concentration. This localized field enhancement accelerates charge trapping and time-dependent dielectric breakdown (TDDB), compromising long-term device reliability.

Impact on Source/Drain Epitaxy

Following gate patterning, active fin extensions undergo selective epitaxial growth (SEG) of raised source/drain structures (e.g., SiGe for pFETs or SiP for nFETs). If the fin recess step produces non-uniform fin heights or damaged surface crystal lattices, epitaxial nucleation becomes non-uniform, leading to stacking faults, facet distortion, or high contact resistance (R_c).

Walk the Real Step

In the complete 14nm integration sequence, this step is specifically executed as part of the active fin exposure module. To examine the exact structural transformation, process parameters, and interactive 3D model of this unit operation, you can Open FIN_RECESS Step 66 in the interactive flow.

This step transitions the substrate from as-etched fin trenches to a precisely recessed silicon fin height, preparing the structure for subsequent sacrificial oxide recess, well implantations, and gate stack formation.

Related Learning Paths

To understand how the fin recess process interacts with the rest of the manufacturing line, explore the comprehensive guide on 14nm FinFET process flow, which details the end-to-end integration logic from substrate preparation to back-end-of-line (BEOL) interconnects.

The fin recess module operates in tight coordination with several adjacent process steps:

• Spacer-Defined Fin Patterning: Sub-diffraction lithography (SADP/SAQP) and deep silicon trench etching that establish initial fin width, pitch, and crystal orientation.
• Sacrificial Oxide Recess: Dielectric wet/dry recess steps that pull down shallow trench isolation oxide to expose the 3D channel sidewalls.
• Punch-Through Stopper (PTS) Implantation: Well engineering steps performed to inject heavy dopants into the sub-fin region, suppressing subsurface leakage paths beneath the active channel.
• Replacement Metal Gate (RMG) Module: Gate-last deposition of high-k gate dielectrics (e.g., HfO2) and work-function metal stacks that conformally wrap the exposed 3D channel profile.

Future Outlook

As logic scaling moves beyond 14nm into sub-3nm gate-all-around (GAA) architectures, traditional fin recess processes are evolving to satisfy sub-nanometer manufacturing tolerances:

• Atomic Layer Etching (ALE): Traditional plasma reactive ion etching is being augmented or replaced by atomic layer etching (ALE) schemes. ALE utilizes self-limiting cyclic surface adsorption and desorption reactions to achieve Angstrom-level depth control without inducing subsurface lattice displacement or plasma damage.
• Transition to Nanosheet Architectures: In gate-all-around (GAA) nanosheets, traditional silicon fin recessing is superseded by sacrificial SiGe selective recessing and nanosheet release processes. However, the fundamental physics of selective dry etching, sidewall passivation, and atomic-scale profile control remain foundational to GAA channel fabrication.
• Heterogeneous Channel Materials: Advanced nodes explore high-mobility channel materials such as SiGe or III-V compounds (InGaAs) integrated on silicon. Recessing these heterogeneous channels requires multi-selective etch chemistries that preserve complex compound interfaces while precisely defining active channel dimensions.