Via-Contact Metal Fill and CMP in 7nm FinFET Integration: Mechanics, Planarization, and Module Interactions

Function in the Complete Flow

In advanced logic manufacturing, the Middle-of-Line (MOL) module acts as the critical electrical and physical bridge connecting sub-surface Front-End-of-Line (FEOL) active transistor structures—specifically the source/drain epitaxial terminals and local gate electrodes—to the Back-End-of-Line (BEOL) multi-level interconnect network [P1, P4]. Within the 7nm FinFET process flow, the via-contact (VC) metal fill and Chemical Mechanical Planarization (CMP) module transforms high-aspect-ratio contact openings into electrically isolated, highly conductive metallic plugs [P1, T1].

This step receives patterned inter-layer dielectric (ILD) structures containing deeply etched via openings exposed down to the source/drain contact silicide and gate contact surfaces [P1, P4]. The core responsibility of this module is to achieve void-free volumetric metal filling (such as a via contact tungsten plug or cobalt fill) and subsequently remove the overburden metal and underlying adhesion barrier films via contact metallization planarization [P1, P2]. The final output of this process step hands off a perfectly coplanar dielectric surface embedded with isolated contact plugs to the first BEOL metal layer (M1) metallization sequence, preventing inter-line electrical shorting and minimizing topography propagation into fine-pitch interconnect levels [P1].

[Etched Contact Vias in ILD]
              │
              ▼
  [Barrier/Liner Deposition (Ti/TiN)]  ──► Protects dielectric & promotes adhesion [P1]
              │
              ▼
    [Bulk Metal Fill (W or Co)]        ──► Fills high-aspect ratio contacts [P1, P2]
              │
              ▼
   [Contact CMP & Buff Polish]         ──► Clears overburden & achieves coplanar surface [P1, P2]
              │
              ▼
[Flat Topography Ready for M1 Damascene]

Upstream Input State

Before entering the metal fill and planarization sequence, the wafer surface inherits complex geometric, mechanical, and material constraints from preceding module steps (Engineering Practice). The 7nm FinFET contact-via integration architecture relies on extreme ultraviolet (EUV) single-exposure lithography and highly anisotropic plasma etching to pattern ultra-tightly spaced contact vias [P4]. Consequently, the incoming dielectric profile features extremely tall sidewalls with high aspect ratios, driven by the vertical dimensions of 3D FinFET fins and multi-work-function replacement metal gate (RMG) stacks [P1, P4].

The physical and surface state inherited at this stage includes:

• Etched Profile Topography: Open via structures with tight Critical Dimension (CD) control, smooth sidewall profiles, and clean landing surfaces over epitaxial silicide layers [P4].
• Barrier and Liner Conformality: A thin titanium/titanium nitride (Ti/TiN) dual-layer liner deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD) covers the via sidewalls and bottom surfaces [P1, A1]. This liner acts as an essential diffusion barrier preventing metal migration into the dielectric while serving as an adhesion promoter for the primary plug metal [P1, T1].
• Surface Residues and Thermal Budget Limits: Prior cleaning treatments clear halogen and oxide residues from silicide interfaces while maintaining strict thermal budget constraints to prevent dopant deactivation in source/drain regions [T2, A1].

The high ratio of depth to width in these narrow contacts severely restricts the physical window for subsequent fill mechanisms, making the wafer highly susceptible to void formation if fill conformality is inadequate [P1, P3].

Physical and Chemical Mechanisms

Metal Deposition Dynamics and Seam Formation

VC metallization CMP 7nm process integration requires absolute void-free gap filling within narrow, high-aspect-ratio contact structures [P1, P3]. Chemical vapor deposition (CVD) of tungsten (W) utilizes reduction reactions of precursor gases (such as tungsten hexafluoride) over a thin ALD TiN nucleation layer [P1, A1]. Because deposition occurs simultaneously from all sidewalls, the growth fronts meet in the center of the contact cavity [P1, T1].

As technology scales to the 7nm FinFET generation, the narrowing via core frequently creates a seam where opposing growth fronts merge [P1]. If reactant gas diffusion becomes limited near the bottom of high-aspect-ratio vias, incomplete merging produces keyhole voids [P1, P3]. To mitigate seam formation, processes employ localized atomic layer deposition techniques or metal reflow strategies (such as cobalt reflow or optimized nucleation steps) that alter the growth kinetics, promoting bottom-up volumetric filling [P2, P3].

Tungsten (W) CVD Fill Mechanism:
┌───┐             ┌───┐             ┌───┐
│   │             │ W │             │ W │
│   │ ──► ALD ──► │   │ ──► Bulk──► │███│ (Seam formation at 
│   │   Nucleation│   │     CVD     │███│  center interface)
└───┘             └───┘             └───┘
 [TiN]             [W Seed]          [Filled Plug]

Chemical Mechanical Planarization Synergy

Once bulk metal deposition completely covers the wafer surface, creating a continuous overburden film, chemical mechanical planarization (CMP) is employed to selectively eliminate the excess metal and barrier layers [P1, T1]. The core mechanism of metal CMP operates on a controlled dual-action paradigm: chemical oxidation/passivation coupled with mechanical shear removal [P1, P2].

  Chemical Slurry Action                   Mechanical Shear Action
┌─────────────────────────┐               ┌─────────────────────────┐
│ H2O2 / Oxidizer reacts  │               │ Colloidal Silica/Alumina│
│ with metal surface      │ ────────────► │ abrasives under pad load│
│ forming passivated oxide│               │ shear away soft oxide   │
└─────────────────────────┘               └─────────────────────────┘
            │                                          │
            └───────────────────┬──────────────────────┘
                                ▼
                   Planarized Surface Profile

1 [P1]. Chemical Softening and Passivation: The CMP slurry contains oxidizers (such as hydrogen peroxide) that react with the surface layer of tungsten or cobalt to generate a chemically weakened, thin surface oxide or complexed passivation film [P1, P2]. 2. Chelating and Complexing Kinetics: Complexing agents (such as carboxylate-bearing organic compounds or tartrate salts) interact with metal oxide cations to form soluble complexes or soft boundary layers [P2]. This chemical modification lowers the mechanical binding energy of the surface layer without causing uncontrolled isotropic chemical corrosion of the static metal inside the contact via [P1, P2]. 3. Mechanical Shear Removal: Under applied downforce stress and relative motion between the polyurethane polishing pad and the wafer substrate, nano-abrasive particles (colloidal silica or alumina) mechanically shear away the chemically softened surface film at high points of topography [P1, P2]. Downward polishing pressure is concentrated on protruding regions, achieving rapid planarization while recessed areas remain protected by the passivated chemical layer [P1].

Multi-Step Polish and Selectivity Engineering

Metal contact planarization planarization typically proceeds through a multi-step polishing scheme to manage material transitions safely [P1, P2]:

• Step 1 (Bulk Metal Overburden Removal): Focuses on high material removal rate of tungsten or cobalt, stopping precisely on or near the underlying Ti/TiN liner [P1]. Slurry chemistry prioritizes high selectivity of bulk metal over barrier material to prevent premature liner erosion [P1].
• Step 2 (Liner and Interface Polish / Buff Step): Employs a dedicated buff slurry designed for co-polishing heterogeneous materials—the remaining metal plug, the Ti/TiN barrier layer, and the surrounding dielectric oxide (such as TEOS or low-k oxides) [P1, P2].

During the buff step, controlling the relative removal rate selectivity among cobalt/tungsten, titanium nitride, and dielectric oxide is paramount [P2]. Imbalanced selectivity leads directly to severe dishing of the soft metal plug or erosion of the adjacent dielectric material [P1, P2].

Downstream Impact and Failure Propagation

Process variations or kinetic imbalances during the VC metallization CMP 7nm sequence propagate severely into downstream BEOL patterning and device electrical operation [P1, P4].

                    ┌───────────────────────────────┐
                    │ Over-polishing / Imbalance    │
                    └───────────────┬───────────────┘
                                    │
            ┌───────────────────────┴───────────────────────┐
            ▼                                               ▼
┌───────────────────────┐                       ┌───────────────────────┐
│    Plug Dishing       │                       │   Dielectric Erosion  │
└───────────┬───────────┘                       └───────────┬───────────┘
            │                                               │
            ▼                                               ▼
┌───────────────────────┐                       ┌───────────────────────┐
│ Depth-of-Focus Deficit│                       │ Metal Shorting at M1  │
│  & Resistance Spikes  │                       │ Fine-Pitch Lithography│
└───────────────────────┘                       └───────────────────────┘

Planarization Deficiencies: Dishing and Erosion

• Metal Dishing: If the CMP slurry exhibits an excessively high chemical removal rate for the metal relative to the dielectric, the polish pad flexes slightly into the center of the contact plug, creating a concave recess [P1, P2]. Dishing increases overall contact resistance ($R_{CNT}$) and introduces local height variations that degrade depth-of-focus during subsequent fine-pitch lithography steps [P1, P4].
• Dielectric Erosion: Excessive mechanical pressure or slurry abrasive aggressiveness toward the dielectric causes uniform lowering of the oxide field surrounding dense contact arrays [P1, P2]. Erosion creates macro-topography variations across the die, leading to residual metal stringers and shorting during the damascene patterning of the first metal layer (M1) [P1].

Physical Seam Exposure and Keyhole Corrosion

If CVD metal deposition leaves an unsealed central seam or internal keyhole void, the polish process will eventually uncap the defect once overburden metal is cleared [P1]. Exposed seams create severe downstream reliability risks: 1 (Engineering Practice). Chemical Trapping: CMP slurry chemistry, surfactant species, and slurry abrasives penetrate open keyholes, resisting post-CMP clean treatments [P1]. 2. Interconnect Voiding: Trapped corrosive chemicals react over time, causing progressive metal voiding, localized electro-thermal stress concentrations, and premature failure under electromigration stress testing [P3, A1].

Walk the Real Step

To see where this specific process step operates within the complete manufacturing sequence of a 7nm FinFET device, inspect the detailed interactive module flow:

Open VC Step 380 in the interactive flow

Within this interactive execution step, observe how the delicate transition from bulk deposition to final buff polishing maintains structural integrity across dense logic arrays and embedded memory SRAM bitcells [P4]. The precise termination of the buff polish step ensures a non-damaged, low-roughness interface critical for low-resistance upper-level via connections [P1, P4].

Related Learning Paths

To further understand how via-contact metallization integrates with adjacent manufacturing operations, explore these closely related process flows:

• Deepen your understanding of full-chip integration rules and FEOL-to-BEOL module dependencies in the comprehensive 7nm FinFET process flow [P4].
• Examine the preceding contact patterning, lithography alignment, and deep dielectric etching mechanisms detailed in the 7nm FinFET contact-via integration process flow [P4].

Future Outlook

As technology scaling pushes beyond the 7nm node into sub-3nm gate-all-around (GAA) nanosheets and complementary FET (CFET) architectures, traditional via contact tungsten plug integration encounters severe resistance scaling limits due to barrier thickness constraints and grain-boundary scattering [P2, P3, A1].

Emerging solutions reshaping contact metallization include:

• Alternative Barrierless Metals: Direct deposition of elemental cobalt (Co) or ruthenium (Ru) eliminates the need for resistive TiN barrier layers, maximizing the net volumetric conductive area of narrow contact vias [P2, P3].
• Selective Metal Deposition: Bottom-up selective ALD of metals eliminates overburden entirely, dramatically relaxing the mechanical demands placed on post-fill CMP processes [P1].
• Backside Power Delivery Networks (BSPDN): Transitioning power contacts to the backside of the silicon wafer requires deep through-silicon or backside contact vias, introducing multi-height planarization challenges that demand advanced, high-selectivity slurry formulations [A1, A2].