A pixel voltage is the result of charge generation, collection, storage, transfer, and conversion. Calling every n-type region photosensitive confuses the photodiode with its readout node. Treating the surface p-type pinning region as extra storage volume also misses its purpose.
Collection and conversion occur at different nodes
Step 54 establishes an n-type photodiode-related region that works with surrounding doping to form junction and potential boundaries. After intervening gate processing, step 93 establishes source/drain and floating-diffusion-related regions. During operation, the transfer gate controls delivery of collected charge to FD. The capacitance at FD turns that charge into a voltage change for the readout circuit.
The regions can share a conductivity type while serving different jobs. Photodiode geometry and potential shape collection and storage. FD capacitance participates in charge-to-voltage conversion. Their fabrication order is not the timing sequence for exposure and readout.
Process checkpoint
Understand N Photocathode Ion Implantation in context
Start at the photosensitive junction and distinguish the FD readout junction from surface pinning.
Process context for “Photodiode, transfer gate and FD: from charge to readout”: 40nm BSI CMOS Image Sensor · PD · Step 54
Pixel sensing and readout: photodiode, diffusion, and pinningWhy add a p-type region at the surface?
Step 99 establishes the surface pinning region. It changes the near-surface boundary and helps control the interaction between surface states and the main storage region, addressing surface-related dark signal. Its purpose is not simply to enlarge the photosensitive volume. Complete transfer also depends on the potential transition toward the transfer gate.
Follow identities across the three drawings
Keep the photodiode location fixed in mind, identify the readout-related region in the second view, and then locate surface pinning in the third. A structural schematic distinguishes regions but does not directly show operating potentials, dark current, or moving charge packets. The central lesson is that low dark signal and effective readout require several boundaries to work together.
Manufacturing order is not pixel operating order
| Operating task | Structure to examine | Question |
|---|---|---|
| Collection and storage | Photodiode | Where does signal charge accumulate? |
| Transfer | Transfer gate and neighboring potential boundaries | Can charge move adequately into the readout node? |
| Charge-to-voltage conversion | Floating diffusion | How much voltage change represents that charge? |
The table describes operating responsibilities. The three images instead show regions being formed during manufacturing. Fabricating the pinning region at Step 99 does not mean a pixel performs a pinning fabrication operation every time it is read.
The n-type photodiode-related region is established in silicon; gate formation and readout-related implants follow later.
Source/drain and FD-related regions appear near the gate structure; distinguish their device roles from the photodiode.
Surface p-type pinning lies above the photosensitive region and controls its surface boundary; it is not another FD node.
When following a weak signal, distinguish too little collected charge, incomplete transfer, and a smaller voltage change for the same received charge. These point to different parts of the chain. Adjusting FD area alone cannot be assumed to resolve all three.
The photodiode should therefore not be judged solely by the size of its visible region, or FD solely by a conversion-gain objective. Their relationship includes the path controlled by the transfer gate. The cross-sections help locate the relevant boundaries, while operating potentials and noise require additional device evidence.
A reader should be able to trace the functional handoff from collection to transfer to voltage conversion without confusing it with the order in which these structures were fabricated.
Sources
References
A Review of the Pinned Photodiode for CCD and CMOS Image Sensors
E. Fossum, Donald B. Hondongwa · IEEE Journal of the Electron Devices Society