CMP dishing describes a conductor surface recessed relative to the nearby dielectric. Erosion describes loss of height in a patterned region relative to a suitable surrounding reference. They can occur together, but they are not interchangeable measurements. The first question is therefore: which two surfaces are being compared?
Two different height comparisons
In a metal damascene example, polishing initially removes metal above the dielectric field. As field metal clears, the contacting surface becomes a mixture of materials and patterns. Mechanical contact and chemical removal continue to interact; reaching the clearing stage does not make every exposed material stop responding.
Dishing becomes visible when metal inside an opening is lower than the adjacent dielectric. Erosion is identified by comparing the patterned region with a reference outside that region. A metal line can have little local recess while the whole surrounding array has lost height. Conversely, a wide metal feature can be recessed without the same regional loss.
| Observation | Relevant comparison | What it does not establish |
|---|---|---|
| Metal below adjacent dielectric | Local metal-to-dielectric height | Total loss across the patterned region |
| Dense region below surrounding field | Regional height difference | The recess of each individual line |
| Remaining metal on the field | Clearing completeness | Absence of dishing elsewhere |
Process checkpoint
Understand M2 Cu CMP in context
Examine how copper planarization separates lines and why local surface shape matters.
Process context for “CMP Dishing vs Erosion: Read the Reference Surface”: 28nm Planar Flow · M2 · Step 224
Why a single explanation is insufficient
A compliant polishing contact can reach into metal features, while different materials respond differently to the same polishing environment. These interactions help explain local recess. Pattern distribution also changes the contact and material-removal environment over a region. Incoming topography, feature geometry and exposure history therefore matter together.
It is tempting to translate this into “wide lines dish, dense lines erode.” That is a useful first illustration, not a complete predictive law. Different regions can enter the clearing stage at different times. The same final height difference can consequently reflect more than one history.
Read three surfaces instead of one
For an educational cross-section, identify the metal surface, its immediately adjacent dielectric, and an external reference field. Keep all three visible when comparing before and after states. Measuring only the metal against the remote field combines local recess and regional loss, hiding which contribution changed.
Consider two sketches with equally low metal tops. In sketch A, the neighboring dielectric remains high. In sketch B, the neighboring dielectric has also moved down. Calling both “the same dishing” loses the most useful distinction. This is a conceptual measurement exercise, not a method for extracting dimensions from an uncalibrated process illustration.
What the next level inherits
The next dielectric and lithography steps inherit the remaining surface, not the intended target plane. Local recess can change conductor geometry and the shape that later films cover. Regional loss can affect planarity across patterns. Neither observation alone proves a particular resistance, leakage or reliability result; those depend on the actual remaining structure and electrical measurements.
The integration objective is therefore not simply “polish less.” Incomplete field clearing can leave unwanted connections, while extra removal may worsen some topographical changes. Understanding both requirements explains why clearing and retained geometry must be evaluated together.
Source links
References
Silicon VLSI Technology - Full
James D. Plummer, Michael D. Deal, Peter B. Griffin
Silicon VLSI Technology · ISBN 978-0130850379