7nm Metal Gate CMP Mechanism: Physical Chemistry, Planarization Stop Control, and Integration Dynamics

Function in the Complete Flow

In advanced replacement metal gate (RMG) FinFET integration, sacrificial poly-silicon dummy gates are removed and replaced with high-k gate dielectrics, multi-layer work function metals, and a low-resistivity bulk fill metal. Chemical mechanical planarization is employed in advanced logic manufacturing because global or near-global planarization can be achieved [T1]. Within this module, Metal Gate CMP serves as the critical geometric boundary definition process that converts overburden metal deposits into isolated, planar gate electrodes.

During the deposition of work function metal stacks and bulk fill tungsten, material coats both the narrow gate trenches and the surrounding dielectric field. This leaves severe surface topography and electrical continuity across all gate lines. The primary objective of Metal Gate CMP is to remove the excess overburden, electrically isolate individual gate lines across dense fin arrays, and establish a uniform, controlled gate height flush with or selectively recessed below the surrounding dielectric surface.

The resulting gate electrode height, surface topography, and work function layer integrity directly control effective gate capacitance, fringe fields, and threshold voltage across NMOS and PMOS devices. If overburden removal is incomplete, adjacent gate lines remain electrically shorted. Conversely, excessive removal lowers the gate electrode height, increasing gate resistance and inducing severe threshold voltage variation across the wafer. A comprehensive understanding of this operation requires viewing it in the context of the overall 7nm FinFET process flow.

+------------------------------------------------------------------+
|                   Upstream Deposition Module                     |
|  - Conformal High-k Dielectric Layer                             |
|  - Multi-Layer Work Function Metal Stacks                        |
|  - Bulk Tungsten Overburden Deposition                           |
+------------------------------------------------------------------+
                                  |
                                  v
+------------------------------------------------------------------+
|               Metal Gate CMP Module (7nm FinFET)                 |
|  - Surface Passivation & Oxidation Mechanics                     |
|  - Micro-Abrasive Mechanical Shear Removal                       |
|  - High Selectivity Stop & Gate Recess Control                   |
+------------------------------------------------------------------+
                                  |
                                  v
+------------------------------------------------------------------+
|                  Downstream Integration Steps                    |
|  - Plasma Ashing & Surface Preparation                           |
|  - Self-Aligned Dielectric Gate Cap Deposition                   |
|  - Middle-of-Line (MOL) Contact Trench Etch & Metallization      |
|  - Multi-Level Interconnect Formation                            |
+------------------------------------------------------------------+

Upstream Input State

Prior to Metal Gate CMP, the wafer presents a complex multi-material topography resulting from preceding etching and deposition sequences. After sacrificial dummy gate removal, atomic layer deposition forms a thin, highly conformal high-k gate dielectric over exposed fin channels. Subsequently, multiple work function metal layers—such as titanium nitride, tantalum nitride, titanium aluminum carbide, or titanium aluminide—are deposited to set the specific threshold voltages for n-type and p-type transistors.

To complete the filling of high-aspect-ratio gate trenches, a bulk fill metal—most commonly tungsten—is deposited using chemical vapor deposition to fill the remaining cavities. Because these metal layers conformally follow the underlying feature topography, the incoming wafer surface exhibits significant elevation differences between dense fin arrays and isolated dielectric regions.

This incoming state presents two major physical challenges for the planarization process:

1. Material Heterogeneity: The surface consists of dissimilar metallic layers with different mechanical hardness values, standard electrochemical potentials, and oxidation reaction rates.
2. Topographical Variations: Local and array-scale step heights require rapid initial planarization without causing excessive erosion in lower-density regions or over-polishing narrow trenches.

The underlying dielectric layer—typically silicon dioxide or silicon nitride—acts as the landing stop layer. Any pre-existing non-uniformities or structural defects from prior deposition or etching steps are inherited directly by the CMP process.

Physical and Chemical Mechanisms

Metal Gate CMP operates through the coupled interaction of chemical surface modification and abrasive mechanical removal at the interface between the polishing pad, slurry, and wafer.

                  Polishing Pad Downforce & Motion
                                 |
                                 v
      +----------------------------------------------------+
      |               Slurry Media & Pad                   |
      |   (Oxidizer, Inhibitors, Complexing Agents, pH)    |
      +----------------------------------------------------+
                                 |
    -----------------------------v-----------------------------
    Chemical Reaction: Surface Metal + Oxidizer -> Oxide Layer
    -----------------------------------------------------------
    Mechanical Shear: Abrasive Impact Shears Softened Oxide
    -----------------------------------------------------------
                                 |
                                 v
                   Planar Metal Gate Electrodes

Chemical Passivation and Surface Reactions

A metal CMP slurry contains oxidizing agents, complexing agents, corrosion inhibitors, dispersion agents, and pH adjustors [P2]. When the aqueous slurry contacts the metal overburden, oxidizers (such as hydrogen peroxide) react with the exposed metals to generate a thin, passivated oxide film at the surface. Complexing agents bind metal ions in solution to control reaction rates, while corrosion inhibitors passivate low-lying surfaces to suppress isotropic dissolution.

For the surrounding dielectric material, removal involves hydration of the surface under specific pH conditions, making the dielectric susceptible to mechanical abrasion.

Mechanical Shear and Removal Kinetics

As the wafer rotates against the polyurethane polishing pad in the presence of sub-micron silica or alumina abrasive particles, contact stress concentrates at elevated topographical peaks. The mechanical shear force exerted by the abrasive particles selectively removes the softened, oxidized metal film from high spots. Once removed, the unreacted underlying metal is exposed to further chemical oxidation, maintaining a continuous oxidation-shear cycle. In recessed regions, lower local contact pressure preserves the passivating film, protecting the metal from premature removal and promoting rapid planarization.

Planarization Stop and Selectivity Mechanisms

In replacement metal gate processing, primary overburden removal is followed by a final tungsten touch-up CMP process with high tungsten-to-oxide selectivity to level off the protruded metal patterns and drive the gate height to final target . High chemical selectivity ensures that once the overburden metal is cleared, removal slows dramatically upon reaching the flat dielectric surface.

The relative material removal rate ratio $S$ between metal and dielectric stop layer can be expressed conceptually as:

$$S_{\text{metal/stop}} = \frac{RR_{\text{metal}}}{RR_{\text{stop}}} = \frac{k_{\text{chem, metal}} \cdot P \cdot V}{k_{\text{chem, stop}} \cdot P \cdot V}$$

where $RR$ represents removal rate, $k_{\text{chem}}$ is the surface chemical reaction rate constant, $P$ is local contact pressure, and $V$ is relative velocity.

Metal Gate Recess Control and Dishing

After the bulk overburden is cleared, the process is tuned to achieve a controlled recess of the metal gate below the dielectric surface. This recess creates space for subsequent dielectric cap deposition.

During recess polish, galvanic corrosion can occur because dissimilar metals (such as tungsten fill and titanium nitride work function liners) are immersed in an conductive aqueous slurry. Differences in standard reduction potentials create galvanic micro-cells, causing accelerated chemical dissolution of the less noble metal. Slurry formulations use complexing agents and inhibitors to balance galvanic potential differences and suppress localized pitting or dishing.

Downstream Impact and Failure Modes

The structural outcome of Metal Gate CMP directly determines the process windows for downstream middle-of-line (MOL) modules.

+---------------------------------------------------------------------------------+
|                         Metal Gate CMP Trade-offs                               |
+---------------------------------------------------------------------------------+
                        |                                 |
                        v                                 v
        [ Over-polishing / Deep Recess ]        [ Under-polishing / Residue ]
                        |                                 |
        +---------------+---------------+                 +-------+-------+
        |                               |                         |
        v                               v                         v
  High Gate Line                 Severe Work Function      Adjacent Gate Shorts &
   Resistance                    Degradation (Vt Shift)    Trench Bridge Defects

Threshold Voltage Uniformity and Gate Resistance

• Over-polishing (Excessive Gate Recess): Reduces the total conductive cross-sectional area of the gate line, which increases high-frequency gate resistance. Furthermore, excessive erosion into upper sidewall work function layers alters the effective work function, leading to threshold voltage ($V_t$) shifts and degraded short-channel control.
• Under-polishing (Incomplete Overburden Clearing): Leaves conductive metallic residues across the field dielectric. This causes electrical shorts between adjacent parallel gate lines, resulting in circuit functionality failure.

MOL Contact Window and Short Circuits

Metal Gate CMP establishes the landing topography for subsequent self-aligned contact (SAC) formation. Excessive dishing of the soft metal fill or array-scale erosion across dense fin patterns creates within-die elevation variations.

During subsequent photolithography, step-height variations that exceed optical depth of focus lead to pattern distortion or overlay misalignment. In subsequent contact etching, non-uniform dielectric cap thickness increases the risk of contact punch-through, which can cause severe electrical shorting between source/drain contacts and gate electrodes. Further context on gate module dependencies can be found in the 7nm replacement metal gate integration process flow.

Process Execution Steps

Execution of Metal Gate CMP in manufacturing follows a multi-stage sequence designed to balance fast overburden removal with precise endpoint control:

1. Bulk Removal Stage: The wafer is polished on a primary platen using high mechanical energy and an aggressive chemical slurry to clear the thick bulk tungsten overburden rapidly.
2. Endpoint Sensing Stage: As the bulk metal clears and underlying work function or dielectric surfaces appear, real-time optical reflectivity or motor torque sensors detect the transition in surface properties, signaling the completion of primary planarization.
3. Over-Polish and Recess Stage: The wafer transitions to a secondary platen with a high-selectivity slurry and reduced mechanical downforce. This stage selectively recesses the gate electrode to the target depth while stopping on the dielectric surface.
4. Post-CMP Clean Stage: The polished wafer is transferred immediately to an integrated cleaning module where megasonic agitation and chemical cleans remove residual abrasive particles and passivate exposed metal surfaces to prevent post-polish corrosion.

The live step implementation can be reviewed in the interactive flow at Metal Gate CMP.

Related Learning Paths

To explore related integration topics across advanced technology nodes:

• Overall Integration Flow: Review the full multi-module sequence in the 7nm FinFET process flow.
• Replacement Metal Gate Module: Detailed chemical etch and metal stack deposition dynamics are covered in the 7nm replacement metal gate integration process flow.

Future Outlook

As device scaling progresses into nanosheet and gate-all-around architectures, gate height control requires atomic-scale precision. Hybrid schemes that combine CMP with atomic layer etching (ALE) or location-specific dry trimming are increasingly studied to decouple overburden removal from final gate recess depth control, minimizing dishing and pattern density effects in advanced nodes.