Function in the Complete Flow
In sub-10nm logic manufacturing, the replacement metal gate (RMG) module replaces sacrificial dummy poly-silicon structures with functional high-k gate dielectrics and multi-layer work function metal stacks , . Within this module, the metal gate chemical mechanical planarization (CMP) step acts as the critical geometric boundary definition process .
The primary function of metal gate CMP in a 7nm fin field-effect transistor (FinFET) architecture is to remove the massive overburden of deposited work function metals and bulk trench fill metals, isolating individual gate lines while restoring planarity across the die , . This step receives a non-planar surface featuring severe topography generated by conformal metal layer deposition over narrow gate trenches and dense fin arrays . Through controlled surface material removal, the CMP step yields electrically isolated, planar gate structures flush with or selectively recessed below the surrounding dielectric surface , .
The output state of this step directly governs the gate height, top surface roughness, and work function metal integrity of both n-type metal-oxide-semiconductor (NMOS) and p-type metal-oxide-semiconductor (PMOS) 7nm FinFET devices . If the planarization process leaves residual metal overburden, adjacent gate lines remain electrically shorted (Engineering Practice). Conversely, excessive material removal reduces the total gate height, driving up high-frequency gate resistance and causing severe threshold voltage variation across the wafer , . Understanding this step within the broader 7nm FinFET process flow is essential for mastering high-yield advanced logic manufacturing .
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| Upstream Deposition Module |
| - Conformal High-k Dielectric (ALD) |
| - Multi-Layer Work Function Metals (NMOS / PMOS WFMs) |
| - Bulk Metal Overburden (Tungsten or Aluminum Fill) |
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| Metal Gate CMP Module (7nm FinFET) |
| - Synergistic Chemical Oxidation & Mechanical Shear |
| - RMG Planarization Stop Mechanism (Dielectric / Hardmask Stop) |
| - Controlled Metal Gate Recess Control |
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| Downstream Integration Steps |
| - Self-Aligned Dielectric Gate Cap Deposition |
| - Middle-of-Line (MOL) Contact Trench Etch & Metallization |
| - Multi-Level Interconnect Formation (M1 / M2 Metallization) |
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Guided route
Metal Gate CMP
This article maps to Chapter 4 (Final gate) of the 7nm FinFET structural spine — 6 stops through the complete flow, each with rationale and 2.5D cross-section evolution.
- 1Active region
- 2Gate coordinates
- 3Source/drain
- 4Final gateThis article
- 5Contacts
- 6Back-end handoff
Upstream Input State
Prior to metal gate CMP, the wafer undergoes complex structural transformations that establish the physical and chemical incoming state , . Following dummy gate removal, atomic layer deposition (ALD) is utilized to deposit thin, highly conformal high-k gate dielectrics such as hafnium oxide across the exposed fin channels , . Subsequently, complex multi-layer work function metal (WFM) stacks are sequentially deposited to define device-specific band alignments .
These WFM stacks typically combine n-type work function metals (such as titanium aluminum carbides, tantalum aluminides, or titanium aluminides) and p-type work function metals (such as titanium nitride or tantalum nitride) to achieve the target threshold voltage for complementary logic circuits . To complete the gate trench filling, a low-resistivity bulk metal overburden—most commonly aluminum or tungsten—is deposited using physical vapor deposition (PVD) or chemical vapor deposition (CVD) to fill the remaining high-aspect-ratio gate cavities , .
Because these multi-layer metallic stacks are deposited conformally over topography, the incoming wafer surface exhibits pronounced elevation differences . Tall feature regions above dense fin arrays support thick metallic topographies, while isolated dielectric regions present deep relief profiles (Engineering Practice).
The physical challenge inherited by the metal gate CMP step is twofold: 1 . Material Heterogeneity: The polishing surface comprises dissimilar metals exhibiting distinct hardness values, electrochemical standard potentials, and oxidation rates . 2. Topographical Non-Uniformity: The incoming film stack exhibits significant step-height variations that must be planarized rapidly without over-polishing adjacent narrow trenches , .
Furthermore, the underlying pre-metal dielectric (PMD) or hardmask layer—typically silicon nitride or silicon dioxide—serves as the structural landing surface , . Any structural non-uniformity or chemical damage induced during upstream chemical vapor deposition or reactive ion etching propagates directly into the CMP removal phase .
Physical and Chemical Mechanisms
The fundamental operation of metal gate CMP relies on the synergistic combination of dynamic chemical oxidation and mechanical shear removal at the slurry-wafer interface , . The classic Prestonian kinetic framework dictates that the removal rate of a given material increases with applied micro-contact pressure and relative sliding velocity, modulated by a chemistry-dependent Preston coefficient . However, at the sub-10nm scale, micro-contact mechanics and surface reaction kinetics dominate the material removal behavior , .
Polishing Motion & Downforce (Pressure P, Velocity V)
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| Polishing Pad & Slurry |
| (Colloidal Abrasives + Oxidizers + Complexing Agents + pH) |
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Chemical Softening: Oxidation & Passivation Layer Formation
Reaction: Metals (W/Al/TiN) + Slurry Oxidizer -> Passivated Metal Oxide Surface
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Mechanical Shear: Micro-abrasive Particle Impact & Removal
Shear Force removes passivated layer; unreacted metal exposed to slurry
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Planar Metal Gate Electrodes
Chemical Passivation and Reaction Kinetics
Metal gate CMP slurries are aqueous formulations containing oxidizers (such as hydrogen peroxide), complexing agents, corrosion inhibitors (such as benzotriazole derivatives), and surfactant additives maintained at specific acidic or basic pH levels , . When the slurry comes into contact with the heterogeneous metal overburden, the oxidizer reacts with the exposed metallic species (e (Engineering Practice).g., tungsten, aluminum, titanium nitride) to form a thin, mechanically weak surface oxide or passivated reaction layer , .
For dielectric surfaces, the removal mechanism is chemically distinct: hydroxyl species in alkaline media hydrate the oxide surface to form a soluble silicate layer, which is then abraded . In advanced gate-last integration, modifying the surface chemical network of the stopping dielectric via ion implantation can passivate surface hydration sites, suppressing chemical softening and enhancing polishing selectivity .
Mechanical Shear and Micro-Contact Dynamics
As the wafer is pressed against a polyurethane polishing pad carrying sub-micron colloidal silica or alumina abrasive particles, high mechanical contact stress concentrates at the elevated topographical peaks , . The abrasive particles selectively shear off the chemically softened metal oxide passivation layer from high spots, exposing underlying pristine metal to further oxidation , . In low-lying recessed regions, lower contact stress prevents abrasive action, allowing the chemical passivation layer to protect the material from dissolution . This dynamic cycle of "chemical oxidation followed by mechanical shear" drives selective planarization , .
RMG Planarization Stop Mechanism
Achieving a reliable RMG planarization stop mechanism requires high removal selectivity between the bulk metal fill/work function stack and the underlying dielectric polish-stop material (such as silicon nitride or PMD oxide) , . High oxide-to-metal or nitride-to-metal selectivity ensures that once the overburden is cleared, the polishing process drastically slows upon encountering the planar dielectric surface , .
The selectivity equation governing surface removal behavior can be conceptually expressed as:
$$S_{\text{metal/stop}} = \frac{RR_{\text{metal}}}{RR_{\text{stop}}} = \frac{k_{\text{chem, metal}} \cdot P \cdot V}{k_{\text{chem, stop}} \cdot P \cdot V}$$
where $RR$ represents the material removal rate, $k_{\text{chem}}$ is the surface-chemical reaction rate constant, $P$ is the micro-contact pressure, and $V$ is the relative polishing velocity , .
Metal Gate Recess Control
Following primary overburden clearing, the process transitions to metal gate recess control . In 7nm replacement metal gate integration, gate electrodes are often intentionally recessed slightly below the PMD top surface to prepare for the subsequent deposition of a dielectric gate cap (e .g., silicon nitride) . Recess depth control relies on fine-tuning the chemical etching component relative to mechanical abrasion , .
A primary physical challenge during recess polish is galvanic corrosion . When dissimilar metals—such as aluminum, tungsten, and titanium nitride work function liners—are simultaneously exposed to an electrolyte slurry, differences in their standard electrochemical reduction potentials create micro-galvanic cells . The metal with the lower reduction potential acts as an anode and undergoes accelerated chemical dissolution, leading to preferential metal pitting or severe dishing of the bulk fill . Formulating slurry chemistry with specific complexing agents and corrosion inhibitors balances the galvanic potential differences, preventing localized recess defects .
Downstream Impact and Failure Propagation
The geometric and chemical outcomes of the metal gate CMP step propagate directly into downstream front-end and middle-of-line (MOL) modules, establishing clear directional trade-offs , .
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| Metal Gate CMP Trade-offs |
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[ Over-polishing / Deep Recess ] [ Under-polishing / Residue ]
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High Gate Line Severe Work Function Adjacent Gate Shorts &
Resistance Degradation (Vt Shift) Trench Bridge Defects
Electrical Resistance and Short-Channel Control
- Over-polishing (Excessive Metal Gate Recess): Reduces the cross-sectional conductive area of the metal gate line . According to classical conduction principles, gate resistance increases inversely with cross-sectional area (Engineering Practice). Higher gate resistance increases RC delay times, degrading high-frequency operational speed in 7nm logic circuits . Furthermore, deep over-polishing can erode the thin work function metal layers along the upper sidewalls of the fin, causing severe threshold voltage ($V_t$) shifts and short-channel control degradation , .
- Under-polishing (Incomplete Overburden Removal): Leaves residual conductive metallic bridges across the dielectric surface (Engineering Practice). This failure mode results in short circuits between neighboring parallel gate lines, causing catastrophic die yield loss (Engineering Practice).
Contact Module Integration Windows
The metal gate CMP process defines the topographic landing surface for subsequent self-aligned contact (SAC) and MOL trench formation . Excessive dishing (where the soft bulk fill metal polishes faster than the surrounding hard dielectric) or field erosion (where dense array patterns polish faster than isolated regions) creates severe within-die (WID) height variations , .
During downstream contact lithography, severe step height variations exceed the depth of focus of extreme ultraviolet (EUV) or immersion lithography systems, causing pattern distortion or photo misalignment , . In subsequent contact etch steps, non-uniform dielectric cap thickness over recessed gates increases the risk of contact hole punch-through, leading to electrical shorting between source/drain contacts and gate electrodes , .
To mitigate these downstream failures, engineers balance slurry removal selectivity, pad hardness, and process endpoint detection to maintain precise metal gate recess control across the entire wafer surface , . Detailed architectural interactions are explored in the 7nm replacement metal gate integration process flow .
Walk the Real Step
To understand how these physical principles are executed in industrial manufacturing, examine the step sequence within the live flow environment (Engineering Practice).
Open RMG Step 221 in the interactive flow
Detailed Execution Phase Breakdown
Phase 1: Bulk Metal Removal
[ High Pressure / Fast Velocity ] --> Rapid removal of bulk fill overburden (W/Al)
Phase 2: Transition & Endpoint Detection
[ Optical / Motor Torque Sensing ] --> Detects exposure of underlying PMD hardmask
Phase 3: Over-Polish & Gate Recess Control
[ Low Pressure / Tuned Slurry ] --> Selective recessing of metal gate stack
Phase 4: Post-CMP Cleaning
[ Dilute Chemical Clean ] --> Removes residual silica abrasives & prevents corrosion
1 . Bulk Metal Removal Phase: The wafer is loaded onto a primary platen equipped with a hard, flat polyurethane pad . High downforce and optimized slurry flow rates drive rapid removal of the thick bulk metal overburden (aluminum or tungsten) using aggressive chemical oxidation and mechanical abrasion , . 2. Interface and Endpoint Detection Phase: As the polishing front clears the bulk metal, underlying work function metal layers and dielectric landing stops are exposed , . Advanced in-situ optical reflection sensors or motor torque monitoring systems detect the real-time change in surface reflectivity and frictional drag . This triggers an immediate transition to a secondary platen or modified polishing pressure . 3. Over-Polish and Gate Recess Phase: On the secondary platen, a softer polishing pad with high-selectivity slurry is utilized . The downforce is reduced to minimize micro-scratching and field erosion . During this phase, the RMG planarization stop mechanism halts removal on the dielectric hardmask while controlled chemical action selectively recesses the metal gate electrode to its target depth , . 4. Post-CMP Clean Phase: Immediately following polishing, the wafer passes to an integrated post-CMP cleaning module . Alkaline or organic acid cleans combined with megasonic agitation remove colloidal abrasive particles from the wafer surface while chemical corrosion inhibitors passivate the newly exposed metal gate surfaces, preventing post-polish galvanic staining or pitting .
Related Learning Paths
To deepen your understanding of nanoscale planarization and gate stack integration, explore these closely related modules:
- Complete Integration View: Examine the full multi-step fabrication sequence in the 7nm FinFET process flow, covering substrate preparation, fin formation, source/drain epitaxy, and back-end-of-line (BEOL) interconnects .
- Replacement Metal Gate Module: Trace the detailed step-by-step chemical etches and deposition modules in the 7nm replacement metal gate integration process flow .
- Middle-of-Line Integration: Understand how metal gate CMP recess control dictates the process window for source/drain contact formation and trench metallization , .
Future Outlook
As logic technology scales beyond the 7nm node into sub-3nm nanosheet and gate-all-around (GAA) architectures, metal gate CMP faces unprecedented physical limitations (Engineering Practice). The shift from vertical FinFET channels to stacked horizontal nanosheets further tightens gate height variation tolerances .
Key research and development vectors include:
- Atomic Layer Etching (ALE) Hybridization: Combining chemical mechanical polishing with atomic-scale isotropic dry etching to decouple overburden planarization from final gate recess depth control, eliminating galvanic dishing altogether .
- Low-k Dielectric Integration in MOL: Introducing fragile low-k materials into pre-metal dielectrics to reduce parasitic gate-to-contact capacitance, demanding ultra-low-downforce CMP slurries and soft, highly compliant polishing pads to avoid mechanical delamination , .
- Novel Work Function Material Systems: Transitioning from binary titanium-based work function metals to complex multi-element refractory alloys, requiring advanced slurry formulations capable of complexing novel metallic elements without inducing selective galvanic corrosion .