LELE divides a target pattern between two lithography-and-etch passes. Each exposure handles a less crowded subset, but overlay and edge placement matter when the subsets are combined. The CON/CB gate-contact sequence in this 7nm Flow contains E1 and E2 imaging and memorization-layer transfer, even though its step names do not spell out LELE.
Where is E1 first recorded?
At step 305, Gate Contact_E1 Lithography defines one set of openings in resist. Subsequent SiON and memorization etches transfer it into the mask stack before the next imaging surface is prepared. The structure retains E1 after its resist is no longer kept. Here, memorization means retaining a pattern; it does not require an unverified special chemical-memory mechanism.
Process checkpoint
Understand Gate Contact_E1 Lithography in context
Distinguish the current resist image from the retained pattern and trace E1 and E2 into the integrated etch.
Process context for “Why expose a 7nm gate contact twice?”: 7nm FinFET · CON · Step 305
LELE gate contacts: combining two patterning passesE2 contributes another part of the pattern
Step 314 creates the second group on the prepared surface. Track the current resist image separately from the pattern already recorded beneath it. In this rendered example, the groups combine contact locations. It would be misleading to describe E2 generically as only a correction or cut applied to E1. The second group is subsequently recorded through its own memorization etch.
Why is an integrated etch still needed?
Step 319 transfers the combined openings downward through device dielectric toward the gate region. The earlier passes assigned and retained locations; this stage develops the final contact cavity. Ashing, cleaning, and metal filling still follow. An opening is not yet a conducting contact.
Does the presence of a spacer make this SADP?
No. Spacer-shrink operations also occur in this sequence, but E1 and E2 still specify the two groups of locations. Typical SADP generates a multiplied pattern from sidewalls around mandrels. The difference lies in what establishes the pattern positions. Classify the role of a spacer rather than its name, and do not label every other multicolor or sidewall-based 7nm sequence as simple LELE.
Read the images by tracking position and storage
Ask which exposure defines a lateral position, then identify the layer that currently records it. The first resist pattern is not the final deep contact opening. The second exposure is not performed by simply repeating the first on an untouched surface. Intermediate transfer and surface preparation let both groups contribute to a later pattern.
E1 defines the first group in the current resist layer before full-depth contact transfer.
The current E2 image and the retained pattern below occupy different levels; both passes contribute contact locations.
At the integrated etch, the question changes from allocating positions to transferring the combined opening downward. That etch does not correct every relative placement error introduced by the exposures. Successful pattern combination also does not finish the contact interface or conductive fill.
The combined pattern is transferred downward into contact cavities before later cleaning and metal filling.
A useful reading check is to identify what would remain if the current resist were removed. Information already recorded below can survive that removal; a resist-only pattern cannot. This is a geometric way to understand pattern memory without inventing a special chemical storage mechanism.
These are three selected states from one verified 7nm gate-contact sequence. They do not establish that every layer or every 7nm process uses the same patterning method. The intervening operations remain part of the full Flow and retain their existing access rules.
Sources
References
Double patterning lithography for 32 nm: critical dimensions uniformity and overlay control considerations
J. Finders, M. Dusa, B. Vleeming, Birgitt Hepp, M. Maenhoudt, Shaunee Cheng et al.