What is the 14nm FinFET semiconductor process flow?

The 14nm FinFET process flow is an advanced semiconductor manufacturing sequence that uses three-dimensional fin-shaped transistor structures instead of planar transistors. The fins provide better electrostatic control of the channel, significantly reducing short-channel effects and leakage current while enabling continued scaling beyond the limits of planar technology.

How does 14nm FinFET differ from 28nm planar technology?

The primary difference is the transistor architecture: 14nm uses 3D fin structures where the gate wraps around the channel on three sides, while 28nm uses traditional planar (flat) transistors. This tri-gate structure provides superior electrostatic control, enabling ~50% power reduction or ~20% performance improvement at the same power. The process flow also introduces new modules like fin patterning (SADP/SAQP), fin recess, and epitaxial source/drain wrapping around fins.

How many process steps are in the 14nm FinFET flow?

The 14nm FinFET process flow on SemiFlows contains 362 detailed process steps, spanning fin formation, gate patterning, source/drain engineering, contact metallization, and back-end-of-line interconnects.

What is SADP in 14nm FinFET manufacturing?

SADP (Self-Aligned Double Patterning) is a lithography technique used in 14nm FinFET manufacturing to create fin patterns at pitches below the resolution limit of single-exposure lithography. It involves depositing a conformal spacer film on mandrel structures, then removing the mandrels to leave spacer pairs that define the fin locations at half the mandrel pitch.

14nm FinFET - 14nm 工艺流程 | SemiFlows

14nm FinFET预览

34STI Liner Deposition 35STI FCVD Oxide Fill 37SiO2 CMP to SiN Stop

+21 步骤

工艺截面图

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本步要点

依赖表面反应受限生长机制的沉积技术能够在高纵横比鳍结构中实现均匀覆盖，确保阻挡和应力效应在整个沟槽轮廓上具有空间一致性 [P2]。

原理展开

器件背景与集成逻辑

STI 衬垫沉积步骤被插入在鳍表面调理工序之后、体介质间隙填充之前，其目的是在 14 nm FinFET 工艺中稳定鳍侧壁和沟槽界面，从而保持鳍几何形貌和电隔离完整性 [P4]。紧前的鳍氧化和聚合物去除步骤会在硅表面留下化学活性位点以及潜在的亚纳米级粗糙度，若不加控制，这些因素会在后续可流动氧化物填充过程中产生不利相互作用，导致应力集中或在致密化过程中出现非均匀氧化 [P4]。在此阶段引入一层共形衬垫，可在晶体硅鳍与 STI 氧化物之间形成化学和机械缓冲界面，直接为下一模块中的无空洞 FCVD 氧化物填充及 CMP 稳定性做好准备 [P4]。这种集成逻辑遵循 STI 的一般原理，即隔离性能是由沟槽几何、界面质量以及介质应力演化共同决定的，而不仅仅取决于填充材料本身 [P4]。