Tungsten Contact Fill and Chemical Mechanical Planarization in 28nm Planar Process Architecture

Function in the Complete Flow

In 28nm planar CMOS architectures, tungsten contact plug formation and subsequent contact chemical mechanical planarization (CMP) form the critical conductive interface connecting front-end transistor terminals to first-level copper interconnects. Situated within the middle-of-the-line (MOL) module, this processing sequence fills deep contact vias that have been etched through the zero-level inter-layer dielectric (ILD0). These contact openings extend down to expose silicide contacts on source/drain regions as well as upper contact surfaces on metal gate structures.

The primary objective of this module is to convert narrow, high-aspect-ratio dielectric openings into isolated, low-resistance metal plugs. After blanket contact metallization fills the vias and coats the dielectric field, contact CMP removes the overburden metal and underlying liner films [T1]. This operation resets the substrate surface to a flat plane where tungsten plugs are co-planar with the surrounding ILD0 dielectric field.

Delivering a flat, residue-free surface is essential for downstream lithography and metal patterning. Topographic variations or residual metal remnants left after contact polishing severely degrade depth of focus during immersion lithography and induce electrical shorting between adjacent interconnect lines. You can trace this module transition within the overall context of the 28nm Planar Process Flow.

Upstream Input State

The incoming wafer state entering contact metallization reflects cumulative topography and surface conditions from preceding lithography, reactive ion etching (RIE), wet cleans, and silicide formation. Deep contact holes etched through the ILD0 exhibit narrow critical dimensions and high aspect ratios. The sidewalls of these vias typically possess minor tapering and nanoscale roughness created during dielectric plasma etching and photoresist strip procedures.

At the bottom of the contact holes, silicide interfaces on source/drain active areas and metal gate upper surfaces are exposed. Because exposed silicide rapidly forms native oxide and collects airborne organic contaminants or etch residues, an in-situ vacuum pre-clean—such as light argon sputtering or reactive plasma treatment—is executed prior to metal barrier deposition to establish low interfacial contact resistance.

Furthermore, the ILD0 field across the wafer exhibits local and global height variations inherited from underlying gate density patterns and preliminary dielectric polish steps. The contact fill and CMP module must accommodate these height variations without causing localized under-polishing or excessive dielectric erosion.

Physical and Chemical Mechanisms

Barrier and Adhesion Layer Deposition

Directly depositing tungsten onto dielectric materials such as silicon dioxide leads to poor film adhesion and risk of delamination. Additionally, during chemical vapor deposition (CVD) using tungsten hexafluoride (WF6), reactive fluorine species can diffuse into the dielectric or attack underlying silicides. To prevent structural degradation, a thin liner stack consisting of titanium (Ti) and titanium nitride (TiN) is deposited first.

The titanium layer acts as an oxygen getter and establishes a low-resistance ohmic contact with the underlying silicide, while the titanium nitride layer serves as a diffusion barrier against fluorine gas and provides a suitable substrate for tungsten nucleation. Advanced physical vapor deposition (PVD) or metal-organic CVD methods are used to maintain continuous sidewall coverage down narrow contact vias.

Nucleation and Bulk Tungsten CVD Fill

Bulk tungsten cannot nucleate uniformly on titanium nitride without an initial nucleation step. A thin tungsten nucleation layer is formed using pulsed CVD or atomic layer deposition (ALD) by alternating exposures of tungsten hexafluoride and silane (SiH4) or diborane (B2H6). This surface-reaction-limited regime ensures continuous, conformal coverage along the deep via sidewalls.

Following nucleation, bulk tungsten fill proceeds via continuous CVD using hydrogen reduction of tungsten hexafluoride:

WF6 + 3 H2 -> W + 6 HF

Hydrogen reduction offers high step coverage, allowing metal to grow inward from all contact sidewalls until the via is completely filled [T1]. As the growing tungsten fronts meet near the center of the via, opposing crystal grains coalesce, often creating a narrow central seam. Optimizing deposition temperature and chamber pressure minimizes the volume of this central seam.

Tungsten CMP Mechanism

Following bulk CVD, a thick tungsten overburden and underlying barrier film cover the entire wafer surface. Contact CMP removes this overburden while achieving global planarization across the substrate [T1]. In metal chemical mechanical polishing, the slurry solution oxidizes the top surface layer, which is subsequently removed by mechanical abrasion [T1].

    [ Slurry Oxidizer (H2O2) ] + [ Nanoscale Abrasive Particles ]
                                 │
                                 ▼
           +-------------------------------------------+
           | Chemical Surface Reaction                 |
           | W + 3 H2O2 ──► WO3 Passivation Layer      |
           +-------------------------------------------+
                                 │
                                 ▼
           +-------------------------------------------+
           | Mechanical Shear (Pad & Abrasive)         |
           | Selectively Shears Surface Topography     |
           +-------------------------------------------+
                                 │
                                 ▼
           +-------------------------------------------+
           | Fresh Tungsten Exposed ──► Cycle Repeats  |
           | Stops at TiN / ILD Dielectric Interface   |
           +-------------------------------------------+

The polishing slurry contains an oxidizing agent, typically hydrogen peroxide (H2O2), and suspended abrasive particles such as silica or alumina. The oxidizer chemically transforms metallic tungsten into a thin, hydrated tungsten oxide layer:

W + 3 H2O2 -> WO3 + 3 H2O

Three-body contact involving pad asperities, nanoscale abrasive particles, and the wafer surface drives controlled material removal across the topography [P3]. Mechanical shear forces generated by relative motion between the pad and wafer selectively remove the softened oxide layer from raised features. The newly exposed tungsten surface is re-oxidized by the slurry, establishing a continuous chemical-mechanical cycle that levels surface features.

A typical contact CMP process uses a multi-platen approach:

1. Bulk Metal Removal: Rapidly removes the main tungsten overburden using a high-rate slurry, stopping near the titanium nitride liner [T1].
2. Liner and Barrier Polish: Clears the titanium/titanium nitride barrier film across the dielectric field with balanced selectivity toward tungsten and ILD0 oxide.
3. Buffing and Post-CMP Clean: A gentle buff step cleans surface residues and micro-scratches. Acidic or specialized pH-balanced chemical formulations prevent galvanic corrosion between the tungsten core and adjacent barrier metals.

Downstream Impact and Failure Propagation

Flaws during tungsten fill or contact CMP directly affect subsequent yield and device reliability:

• Tungsten Dishing and Dielectric Erosion: Excessive chemical action relative to mechanical abrasion causes dishing of the tungsten plug below the dielectric surface. Conversely, dense contact regions can experience dielectric erosion. During polishing, defects such as dishing, dielectric erosion, scratching, and localized corrosion can degrade device yield and interconnect reliability [P1].
• Metal Residue Shorts: Inadequate polishing time or non-uniform downforce leaves residual tungsten or TiN patches across the ILD0 field, causing short circuits between adjacent contact plugs.
• Seam Opening and Chemical Trapping: If bulk tungsten deposition leaves a wide central seam, polishing can breach the top of the seam. Trapped slurry components or cleaning fluids may outgas during subsequent thermal steps, inducing voiding in upper copper lines.
• Galvanic Corrosion: Potential differences between the tungsten core and titanium nitride liner in wet chemical environments can cause localized plug recess, altering contact resistance.

+-----------------------+----------------------------------+-------------------------------------+
| Failure Mode          | Mechanism                        | Downstream Impact                   |
+-----------------------+----------------------------------+-------------------------------------+
| Plug Dishing          | Unbalanced slurry selectivity    | Photolithography depth-of-focus loss|
| Residual Metal        | Under-polishing / non-uniformity | Inter-plug electrical shorts        |
| Seam Chemical Trapping| Deep seam breach during CMP      | BEOL outgassing and line voiding    |
| Galvanic Recess       | Electrochemical potential delta  | Elevated contact resistance         |
+-----------------------+----------------------------------+-------------------------------------+

Walk the Real Step

To see how this planarization operation fits within the broader manufacturing sequence, inspect the step details in the process flow:

Open CT Tungsten CMP in the interactive flow

This step converts blanket deposited metal overburden into discrete, co-planar contact plugs. Executing this step cleanly ensures that subsequent inter-metal dielectric deposition and damascene metallization proceed on a planar surface. For surrounding context on contact patterning and interface preparation, refer to the 28nm Planar Contact Formation Process Flow.

Related Learning Paths

To explore related contact modules and integration principles in planar logic manufacturing, consult these dedicated guides:

• 28nm Planar Contact Formation Process Flow: Detailed coverage of contact via patterning, plasma etching, silicide interface formation, and liner deposition.
• 28nm Planar Process Flow: Comprehensive architectural overview covering front-end active isolation, replacement metal gate processing, MOL contact integration, and BEOL copper metallization.

Future Outlook

As CMOS nodes scale beyond 28nm into FinFET and gate-all-around architectures, tungsten contact fill faces physical constraints. Shrinking contact dimensions increase the volume fraction occupied by the resistive TiN barrier layer, driving up overall contact resistance.

To address this limitation, advanced nodes incorporate alternative metals such as cobalt (Co) or ruthenium (Ru) for MOL contact fill. These materials enable ultra-thin or barrierless liner interfaces and reduce seam formation when deposited via ALD. Furthermore, selective metal deposition processes are being developed to grow contact fill directly from the bottom of the via, reducing reliance on heavy CMP overburden removal while retaining foundational chemical-mechanical polishing principles.