Tungsten Contact Fill and Chemical Mechanical Planarization in 28nm Planar Process Architecture

Function in the Complete Flow

In the 28nm Planar integration architecture, tungsten (W) contact plug formation and subsequent contact chemical mechanical planarization (CMP) serve as the bridge between front-end of the line (FEOL) transistor devices and back-end of the line (BEOL) copper interconnect levels [P1, T1]. Positioned within the middle of the line (MOL) module, this processing sequence receives patterned contact vias etched through the zero-level inter-layer dielectric (ILD0) [A2]. These open contact holes expose conductive nickel-platinum silicide terminals at the source/drain regions as well as the upper surfaces of replacement metal gate structures [A2].

The primary functional objective of this module is to transform deep, high-aspect-ratio contact openings into discrete, low-resistance, electrically isolated conductive plugs [P1, T1]. W contact plug formation delivers dense, defect-free metal filling across high-density transistor layouts [P4]. Immediately following metal fill, contact metallization CMP 28nm processing removes the overburden of blanket tungsten and adhesion/barrier films from the dielectric field area [P1, A1]. This creates a completely planar surface topography where isolated tungsten plugs sit flush with the surrounding ILD0 surface [P1, T1].

This module hands off an ultra-flat, planar surface to the subsequent first metal level (M1) damascene module [P1]. Without successful tungsten plug planarization mechanism execution, the incoming surface topography would severely degrade subsequent immersion lithography depth of focus and induce metal stringer defects during M1 patterning [P1, T2]. Understanding this transition is essential when analyzing the complete 28nm Planar process flow (Engineering Practice).

Upstream Input State

The incoming wafer state entering W contact plug formation exhibits complex physical and surface conditions inherited from preceding lithography, reactive ion etching (RIE), wet cleans, and silicidation steps [A1, A2]. The contact openings etched into the ILD0 feature high aspect ratios with narrow critical dimensions dictated by the 28nm design rules [P1, P4]. The sidewall profile of these contact openings exhibits slight taper and surface roughness resulting from dielectric RIE chemistry and polymer passivation removal [P4].

At the bottom of the contact vias, the underlying metal silicide layers on active source/drain regions and the top surfaces of metal gates are exposed [A2]. These exposed interfaces are highly susceptible to native oxide growth, organic residues, and fluorine contamination from prior plasma etch steps [A1]. Consequently, an in-situ pre-clean treatment (such as a light argon sputter clean or dry reactive pre-clean) is mandatory prior to metal barrier deposition to ensure low contact resistance [A1].

Additionally, the incoming ILD0 dielectric field is not inherently flat; it inherits underlying gate topography and density-dependent variations from prior dielectric deposition and preliminary ILD polish steps [P1]. The contact metallization module must accommodate both local aspect-ratio variations and macro-scale dielectric height differences to prevent local under-polishing or severe dielectric erosion [P1].

Physical and Chemical Mechanisms

Barrier and Adhesion Layer Deposition

Direct deposition of tungsten onto dielectric materials such as silicon dioxide or carbon-doped oxides results in poor adhesion and catastrophic film peeling [P4, T1]. Furthermore, during subsequent chemical vapor deposition (CVD) of tungsten using tungsten hexafluoride gas, fluorine species can diffuse into the dielectric or react violently with underlying silicides, causing structural degradation known as volcano defects [P4].

To overcome these interface challenges, a thin barrier and adhesion layer system—typically consisting of titanium (Ti) and titanium nitride (TiN)—is deposited prior to tungsten fill [P1, P4, T1]. The titanium film acts as a getter for residual oxides and forms a low-resistance contact with the silicide, while the titanium nitride layer serves as an effective diffusion barrier against fluorine attack and promotes tungsten nucleation [P1, P4]. Advanced physical vapor deposition (PVD) or metal-organic CVD techniques are employed to ensure continuous conformal coverage along the narrow contact sidewalls without choking off the top opening [P4].

Pulsed CVD and ALD Nucleation

Bulk tungsten fill cannot nucleate directly on titanium nitride with uniform grain distribution and low incubation time [P4]. A thin tungsten nucleation layer is required before bulk filling [P4]. Traditional continuous CVD nucleation using silane reduction of tungsten hexafluoride suffers from poor step coverage in scaled, high-aspect-ratio features, causing early pinch-off at the top of the contact hole [P4].

To achieve conformal nucleation in 28nm structures, atomic layer deposition (ALD) or pulsed chemical vapor deposition (pulsed CVD) is implemented [P4]. In pulsed CVD, the deposition chamber undergoes cyclic gas pulsing: brief simultaneous exposure of tungsten hexafluoride and silane, followed by an inert gas purge, a separate silane exposure cycle, and a final purge [P4]. This time-sequenced surface reaction transitions the nucleation process from mass-transport-limited growth to surface-reaction-controlled growth [P4]. The self-limiting nature of surface adsorption ensures highly uniform nucleation layer coverage down the entire depth of the contact hole while maintaining high throughput compared to pure ALD [P4].

Bulk Tungsten CVD Fill

Once the nucleation layer is established, bulk W contact plug formation proceeds via continuous CVD using hydrogen reduction of tungsten hexafluoride [P4, T1]. The overall chemical reaction is governed by:

$$\text{WF}_6 + 3\text{H}_2 \rightarrow \text{W} + 6\text{HF}$$

Hydrogen reduction provides superior step coverage and conformality compared to silane reduction [P4]. During this growth phase, tungsten grains grow inward from the contact sidewalls until they coalesce in the center of the via [P1, P4]. Because growth proceeds simultaneously from all sidewalls, opposing grain boundaries meet in the center, frequently forming a vertical central seam or internal void [P1, P4].

Optimizing thermal energy, gas flow ratios, and total chamber pressure during bulk fill balances deposition rate against seam volume [P4]. Minimizing seam size is critical because wide seams act as traps for polishing slurry and cleaning chemicals during subsequent contact CMP [P1, P3].

Tungsten Polish and Planarization Mechanism

Following bulk CVD, a substantial overburden of blanket tungsten and underlying barrier films covers the entire wafer surface [P1, T1]. The contact CMP module removes this overburden while achieving global surface planarization [P1]. The tungsten plug planarization mechanism relies on a synergistic dynamic between chemical surface passivation and mechanical abrasive shear, consistent with the fundamental principles of chemical mechanical planarization [P1].

    [ Slurry Oxidizer (H2O2) ] + [ Abrasive Particles (Silica/Alumina) ]
                                 │
                                 ▼
           +-------------------------------------------+
           | Chemical Surface Reaction                 |
           | W + Oxidizer ──► WO3 Passivation Layer   |
           +-------------------------------------------+
                                 │
                                 ▼
           +-------------------------------------------+
           | Mechanical Shear (Polish Pad + Abrasive)   |
           | Selectively Shears High Topography Oxide  |
           +-------------------------------------------+
                                 │
                                 ▼
           +-------------------------------------------+
           | Fresh Tungsten Exposed ──► Cycle Repeats  |
           | Stops at TiN / ILD Dielectric Interface   |
           +-------------------------------------------+

During tungsten polish, the polishing slurry contains an oxidizing agent (typically hydrogen peroxide) combined with sub-micron abrasive particles (such as colloidal silica or fumed alumina) suspended in an aqueous medium [P1, P3]. The oxidizer chemically reacts with the exposed metallic tungsten surface to form a thin, mechanically soft tungsten oxide passivation layer [P1, P3]:

$$\text{W} + 3\text{H}_2\text{O}_2 \rightarrow \text{WO}_3 + 3\text{H}_2\text{O}$$

Under the applied downforce of the polishing head and relative rotational motion across the polyurethane polishing pad, abrasive particles selectively contact the high points of the surface topography [P1]. The micro-contact stress shears away the softened tungsten oxide layer [P1]. The newly exposed metallic tungsten is immediately re-oxidized by the slurry chemistry, and the chemical-mechanical cycle repeats continuously [P1]. In low-recessed areas, mechanical shear stress is significantly lower, allowing the passivation layer to protect the underlying metal from rapid chemical dissolution [P1, P3].

The W CMP architecture typically comprises a multi-platen sequence [P1, P3]:

1. Bulk Tungsten Removal (Platen 1): Rapidly clears the thick tungsten overburden using high removal rate slurry, stopping on or near the underlying titanium nitride barrier film [P1, P3].
2. Barrier/Liner Polish (Platen 2): Removes the titanium/titanium nitride barrier film across the dielectric field with controlled selectivity toward tungsten and the ILD0 oxide [P1, P3].
3. Buffing and Clean (Platen 3): A low-downforce buff polish step removes residual native oxides, smooths microscopic micro-scratches, and prepares the surface for post-CMP cleaning [P1, P3].

Controlling post-polish pH environments is vital; while alkaline buffing is traditional in dielectric polishing, tungsten exhibits enhanced electrochemical corrosion and plug recess under alkaline conditions due to the formation of soluble tungstate ions [P3]. Utilizing acidic buff slurries suppresses galvanic corrosion between tungsten and adjacent barrier layers, securing recess-free plug surfaces [P3].

Downstream Impact and Failure Propagation

Process variations or marginalities introduced during tungsten fill and contact CMP directly propagate into severe downstream yield losses and reliability failures:

• Tungsten Plug Dishing and Dielectric Erosion: If the CMP slurry selectivity favors tungsten removal over the ILD0 dielectric, excessive tungsten removal occurs inside the contact via, resulting in dishing [P1]. Conversely, over-polishing high-density contact arrays can remove excess dielectric material, causing local erosion [P1]. Dishing and erosion create topographic depressions that cause depth-of-focus errors during M1 lithography, leading to pattern distortion, bridging shorts, or thin interconnect metal lines with high resistance [P1, T1].
• Metal Residue and Stringer Shorts: Inadequate polish time or non-uniform CMP downforce distribution leaves residual tungsten or titanium nitride patches across the dielectric field [P1, A1]. These conductive remnants create electrical short-circuits between adjacent, independent contact plugs [P1].
• Central Seam Keyholing and Slurry Trapping: Wide central seams formed during incomplete bulk tungsten CVD fill can be opened during the planarization polish [P1, P4]. Acidic polish slurries and chemical cleans become entrapped inside these keyholes [P1, P3]. Subsequent thermal processing during BEOL metallization causes outgassing of trapped liquids, generating voiding in overlying copper M1 lines, localized corrosion, and severe electromigration failure under electrical bias [P1, T1].
• Galvanic Corrosion and Plug Recess: Electrochemical potential differences between the tungsten core, the titanium nitride liner, and the polishing solution can induce localized galvanic corrosion [P3]. Severe corrosion causes tungsten plug recess below the ILD0 surface, increasing contact resistance variance and degrading transistor drive current [P3].

+--------------------------+-------------------------------------+---------------------------------------+
| Flaw Mode                | Root Cause                          | Downstream Mechanism & Failure        |
+--------------------------+-------------------------------------+---------------------------------------+
| Excessive Dishing        | Low W-to-dielectric selectivity     | Depth-of-focus defocus; M1 shorts     |
| Metal Residue / Stringer | Under-polishing; non-uniform force | Inter-plug electrical bridging        |
| Keyhole Seam Entrapment  | Premature CVD fill pinch-off        | Outgassing; M1 voiding; EM failure    |
| Corrosion Plug Recess    | Galvanic mismatch in post-clean pH  | High contact resistance; I_on degradation |
+--------------------------+-------------------------------------+---------------------------------------+

Walk the Real Step

To explore where this specific step sits within the entire middle-of-the-line integration sequence, inspect the interactive process flow:

Open CONTACT Step 187 in the interactive flow

Step 187 represents the definitive planarization boundary where raw deposited metal overburden is converted into high-density, isolated contact plugs [P2]. Proper execution of this step guarantees that the subsequent dielectric deposition and damascene patterning for the M1 level proceed on a pristine, flat substrate [A2]. Additional details on preceding dielectric etching and silicide formation can be referenced in the 28nm Planar Contact Formation Process Flow: Integration Principles, Mechanisms, and Module Dependencies [T2].

Related Learning Paths

To deepen your understanding of how contact metallization integrates with adjacent modules in planar CMOS manufacturing, explore these detailed guides:

• 28nm Planar Contact Formation Process Flow: Integration Principles, Mechanisms, and Module Dependencies: Detailed analysis of contact via patterning, RIE, silicide interface engineering, and barrier deposition [T2].
• 28nm Planar Process Flow: Integration Logic, Device Physics, and Module Dependencies: Comprehensive holistic architecture overview tracing the sequence from initial STI substrate isolation through FEOL replacement metal gate, MOL contacts, and BEOL copper interconnects [T2].

Future Outlook

As device technology scales beyond the 28nm node into advanced FinFET and gate-all-around architectures, classic W contact plug formation and CMP face severe physical limits [P1, P4]. The intrinsic bulk resistivity of tungsten, coupled with the mandatory thickness of the titanium nitride barrier layer, causes contact resistance to skyrocket as contact diameters shrink [P2].

To overcome these resistance bottlenecks, advanced scaling nodes transition from tungsten to alternative metals such as cobalt (Co) or ruthenium (Ru) for contact fill [P3]. Cobalt and ruthenium can be deposited seam-free using pure ALD processes with extremely thin or barrierless interfaces, significantly reducing parasitic MOL contact resistance [P4]. Additionally, selective metal deposition techniques are emerging to eliminate CMP-induced dishing and erosion entirely by growing contact metals bottom-up exclusively inside the via opening [P1]. Nevertheless, the chemical-mechanical planarization principles developed for 28nm W CMP remain foundational for modern multi-material planarization schemes across all advanced semiconductor technology nodes [P1].