Principles of Selective SiGe Epitaxy in 28nm Source-Drain Integration

Function in the Complete Flow

In advanced p-type metal-oxide-semiconductor (pMOS) field-effect transistors within the 28nm Planar Flow, enhancing carrier transport without physically scaling the gate length requires channel band-structure engineering. As physical gate dimensions shrink, classic electrostatic controls degrade, leading to subthreshold leakage and reduced drive current margins. To counteract carrier velocity saturation and mobility degradation in scaling, local strain engineering is introduced directly into the source/drain regions.

Within the overall 28nm Planar process flow, selective silicon-germanium (SiGe) epitaxy acts as the primary mechanical stressor for pMOS devices. The epitaxial source/drain module is integrated into the transistor flow after extension and halo formations but prior to interlayer dielectric deposition [P1]. This step directly follows the formation of recessed source/drain (S/D) cavities and critical surface cleaning operations. In selective epitaxial deposition, material growth is confined to exposed silicon regions while suppressing nucleation on surrounding dielectric films such as silicon dioxide or silicon nitride [T1].

+-------------------------------------------------------------------------+
|                      Upstream Cavity Etch & Clean                       |
|          (Exposed (100)/(111) Si facets; Dielectric Spacers)            |
+-------------------------------------------------------------------------+
                                     |
                                     v
+-------------------------------------------------------------------------+
|                Selective Epitaxial Growth (SEG) of SiGe                 |
|      - Chemical vapor deposition (CVD) precursor adsorption             |
|      - Selective etching competition via halogenated co-reactants        |
|      - Pseudomorphic lattice matching -> Longitudinal compressive strain |
+-------------------------------------------------------------------------+
                                     |
                                     v
+-------------------------------------------------------------------------+
|                        Downstream S/D Module                            |
|          (In-situ boron activation, extension implants,                 |
|          silicidation/contact formation, PMD oxide deposition)          |
+-------------------------------------------------------------------------+

By constraining the larger SiGe crystal lattice within the crystalline silicon host, a strong uniaxial compressive stress field is generated along the longitudinal transport direction of the pMOS channel. This compressive strain splits the heavy-hole and light-hole valence subbands, reducing the hole effective mass and suppressing intervalley carrier scattering, which directly boosts hole mobility and transistor drive current. Highly activated source/drain stressors are essential in transistor scaling to achieve low parasitic series resistance [P2]. Once the embedded SiGe source-drain structure is grown and in-situ doped with acceptor impurities (boron), the substrate is handed off to downstream steps within the 28nm Planar source-drain integration process flow, such as thermal activation and self-aligned silicidation.

Upstream Input State

Before selective epitaxy can occur, the 28nm wafer surface must meet strict chemical, physical, and structural preconditions:

1. Recessed Cavity Geometry and Crystallography

The incoming substrate features exposed single-crystal silicon in the S/D regions, recessed via an anisotropic plasma etch followed by a crystallographic wet etch. This dual-etch sequence creates precise cavity profiles, typically bounded by stable (111) crystallographic facets near the channel edge. The proximity of these (111) facets to the gate edge dictates the geometric coupling efficiency of the lateral compressive strain transferring into the channel region.

2. Dielectric Surface Masking

The gate electrode stack—comprising high-k dielectric layers, metal work-function layers, and polycrystalline silicon—is fully encapsulated by dielectric sidewall spacers (typically composed of silicon nitride and silicon dioxide). Shallow trench isolation (STI) oxides surround the active area boundaries. These oxide and nitride surfaces must remain unreactive to silicon and germanium adatoms during epitaxy to prevent amorphous or polycrystalline deposition outside the S/D regions.

3. Surface Termination and Native Oxide Removal

Chemical vapor deposition (CVD) epitaxy is sensitive to native oxides and atomic-scale surface contaminants. Prior to entering the epitaxy reaction environment, the exposed silicon surface undergoes dilute hydrofluoric acid wet cleaning followed by an in-situ thermal hydrogen bake or chemical clean. This step removes native silicon dioxide (SiO2), leaving an atomically clean, hydrogen-terminated silicon substrate. Any residual oxide islands act as nucleation sites for stacking faults or cause epitaxy failure.

Physical and Chemical Mechanisms

The selective epitaxial growth mechanism in 28nm source-drain integration relies on balancing thermodynamics, surface kinetics, and gas-phase chemical reactions during precursor delivery.

1. Precursor Reaction Chemistry and Gas-Phase Kinetics

SiGe deposition is typically carried out using precursor chemistry consisting of dichlorosilane (SiH2Cl2) or silane (SiH4), germane (GeH4), hydrogen gas (H2) carrier, and hydrochloric acid (HCl) gas as a selective etching agent. The basic heterogeneous decomposition reactions occurring at the hot single-crystal silicon surface can be expressed as:

SiH2Cl2 (g) <-> Si (s) + 2 HCl (g)

GeH4 (g) <-> Ge (s) + 2 H2 (g)

During deposition, gaseous species adsorb onto the clean silicon substrate, diffuse across surface terraces, and incorporate into active lattice kink sites.

2. Kinetics of Selectivity Control

Selectivity between single-crystal silicon and insulating dielectric films (spacers and STI) is maintained by competitive adsorption and etching kinetics. On dielectric materials such as SiO2 or Si3N4, adatoms have low binding energy, long incubation times for stable nucleus formation, and high surface mobility.

By injecting HCl gas into the reaction environment, adatoms or micro-nuclei attempting to deposit on dielectric surfaces are selectively etched away before forming a continuous film. On single-crystal silicon, adatoms quickly incorporate into the host lattice, where the etching rate by HCl is significantly lower than the growth rate. The balance of growth and etching rates determines the process window for defect-free selective epitaxy.

               [ Precursor Gas Phase: SiH2Cl2 + GeH4 + HCl + H2 ]
                                 |
        +------------------------+------------------------+
        |                                                 |
        v                                                 v
[ Exposed Single-Crystal Si ]                     [ Dielectric Surface ]
 (High binding energy)                             (Low binding energy)
        |                                                 |
        v                                                 v
[ Rapid Adatom Incorporation ]                   [ High Rate of HCl Etching ]
        |                                                 |
        v                                                 v
[ Pseudomorphic Crystal Growth ]                   [ Zero Deposition / Clean ]

3. Lattice Mismatch Strain Engineering Mechanics

Germanium possesses a larger covalent atomic radius and lattice constant than silicon. When a dilute alloy of Si(1-x)Ge(x) is grown epitaxially on a rigid silicon substrate, the deposited film is forced to conform laterally to the smaller lattice parameter of the substrate. This pseudomorphic growth state induces biaxial compressive strain within the SiGe film itself.

Because the SiGe structure is bounded by substrate below and open air above, it relaxes vertically (out-of-plane expansion) while exerting a lateral reaction force against the adjacent channel region. This mechanism forms the core of pMOS strain engineering, delivering a longitudinal uniaxial compressive stress directly under the gate dielectric.

The channel stress magnitude can be expressed qualitatively through elasticity theory as a function of the Ge mole fraction (x) and the proximity of the SiGe facet to the channel edge:

sigma_channel ~ E * epsilon_mismatch * f(geometry)

where epsilon_mismatch is proportional to x_Ge.

4. Crystallographic Faceting and In-Situ Doping

During SiGe deposition, growth kinetics vary across crystal planes. Growth along the (111) facet is generally slower than along the (100) plane due to differences in surface atom density and bond configuration. This kinetic anisotropy naturally generates characteristic (111) faceting along the top edges near the spacer wall.

Simultaneously, diborane (B2H6) is introduced to achieve in-situ p-type doping. Incorporating boron during epitaxy yields high electrically active acceptor concentrations without needing high-energy ion implantation steps that could damage the crystal lattice or relax accumulated strain.

Downstream Impact and Failure Propagation

Process variations or kinetic imbalances during selective epitaxy ripple downstream through the 28nm manufacturing module:

+-------------------------------------------------------------------------+
|                    Selective Epitaxy Defect Modes                       |
+-------------------------------------------------------------------------+
       |                                   |                              |
       v                                   v                              v
[ High Ge / Exceeded h_c ]     [ Excess HCl / Low Temp ]      [ Loss of Selectivity ]
       |                                   |                              |
       v                                   v                              v
[ Misfit Dislocations ]            [ Facet Voiding ]             [ Poly-SiGe on Spacers ]
       |                                   |                              |
       v                                   v                              v
[ Complete Strain Relaxation ]     [ High Contact Resistance ]   [ Gate-to-S/D Short Circuit ]
       |                                   |                              |
       v                                   v                              v
[ Degradation of Hole Mobility ]   [ High Series Resistance ]    [ Total Die Yield Loss ]

1. Lattice Misfit Dislocations and Strain Relaxation

If the Ge concentration exceeds the critical pseudomorphic limit for a given film volume, the accumulated elastic strain energy exceeds the formation energy of structural dislocations. The crystal lattice relaxes by generating misfit and threading dislocations. Strain relaxation destroys the channel compressive stress field, dropping hole mobility back to un-strained silicon levels. Furthermore, threading dislocations that intersect the reverse-biased source/drain p-n junction act as generation-recombination centers, causing high off-state junction leakage.

2. Loss of Deposition Selectivity

If the partial pressure of HCl is too low or surface contaminants alter adatom kinetics, selective epitaxy degrades. Amorphous or polycrystalline SiGe nodules nucleate on silicon nitride spacers. During subsequent self-aligned silicide processing, these metallic or conductive poly-SiGe residues bridge the gate-to-source or gate-to-drain gap, resulting in short circuits and catastrophic yield loss.

3. Facet Voiding and Contact Resistance Degradation

Imbalanced facet growth rates can create structural voids at the interface between the SiGe fill and the gate sidewall spacer. Downstream silicidation steps fail to uniformly wet these sub-surface voids. This produces high parasitic series resistance and contact resistance, degrading transistor drive current even if local channel strain remains high.

Walk the Real Step

To explore where this selective deposition operation sits within the interactive manufacturing sequence, view the full module integration context in the software environment:

• Open SD Step 100 in the interactive flow

In Step 100 of the 28nm source-drain module, selective epitaxy transforms the exposed crystalline cavities into operational strain sources. Operating in a chemical vapor deposition environment, the process balances gas delivery, thermal conditions, and selectivity controls to grow heavily boron-doped SiGe S/D structures without nucleating unwanted poly-silicon-germanium on nearby oxide or nitride regions.

Related Learning Paths

To build a complete understanding of front-end and middle-of-line integration within the 28nm Planar Flow, consider these related process flows and engineering analyses:

• 28nm Planar process flow: A comprehensive overview of high-k/metal gate (HKMG) integration, well formation, halo/extension implants, and back-end-of-line handoffs.
• 28nm Planar source-drain integration process flow: A detailed breakdown of cavity etching, surface preparation, selective SiGe epitaxy, and contact silicidation modules.