Principles of Selective SiGe Epitaxy in 28nm Source-Drain Integration

<article> ## Function in the Complete Flow

In advanced p-type metal-oxide-semiconductor (pMOS) field-effect transistors within the 28nm Planar Flow, enhancing carrier transport without physically scaling the gate length to unmanageable levels requires aggressive band-structure engineering [T1]. As physical gate dimensions shrink, classic electrostatic controls degrade, leading to high subthreshold leakage and reduced drive current margins [T1]. To counteract carrier velocity saturation and mobility degradation in scaling, local strain engineering is introduced directly into the source/drain regions [P2].

Within the overall 28nm Planar process flow, selective silicon-germanium (SiGe) epitaxy acts as the primary mechanical stressor for pMOS devices [P1]. This step directly follows the formation of recessed source/drain (S/D) cavities (often etched into specific geometric contours such as sigma-shaped profiles) and critical surface cleaning operations (Engineering Practice). The primary function of selective epitaxy is to fill these recessed crystalline cavities with a pseudomorphic SiGe alloy that has a larger intrinsic lattice constant than the underlying silicon substrate [T1, A2].

+-------------------------------------------------------------------------+
|                      Upstream Cavity Etch & Clean                       |
|          (Exposed (100)/(111) Si facets; Dielectric Spacers)            |
+-------------------------------------------------------------------------+
                                     |
                                     v
+-------------------------------------------------------------------------+
|                Selective Epitaxial Growth (SEG) of SiGe                 |
|      - Chemical vapor deposition (CVD) precursor adsorption             |
|      - Selective etching competition via halogenated co-reactants        |
|      - Pseudomorphic lattice matching -> Longitudinal compressive strain |
+-------------------------------------------------------------------------+
                                     |
                                     v
+-------------------------------------------------------------------------+
|                        Downstream S/D Module                            |
|          (In-situ boron activation, extension implants,                 |
|          silicidation/contact formation, PMD oxide deposition)          |
+-------------------------------------------------------------------------+

By constraining the larger SiGe crystal lattice within the crystalline silicon host, a strong uniaxial compressive stress field is generated along the longitudinal transport direction of the pMOS channel [P1, T1]. This compressive strain splits the heavy-hole and light-hole valence subbands, reducing the hole effective mass and suppressing intervalley carrier scattering, which directly boosts hole mobility and transistor drive current [P1, P2]. Once the embedded SiGe source drain 28nm structure is grown and in-situ doped with acceptor impurities (boron), the substrate is handed off to downstream steps within the 28nm Planar source-drain integration process flow, such as extension halo implants, thermal activation, and self-aligned silicidation [P1, A1].

Upstream Input State

Before selective epitaxy can occur, the 28nm wafer surface must meet strict chemical, physical, and structural preconditions:

1 [P1]. Recessed Cavity Geometry and Crystallography

The incoming substrate features exposed single-crystal silicon in the S/D regions, recessed via an anisotropic plasma etch followed by a crystallographic wet etch (Engineering Practice). This dual-etch sequence creates precise cavity profiles, typically bounded by stable (111) crystallographic facets near the channel edge [P1, P3]. The proximity of these (111) facets to the gate edge dictates the geometric coupling efficiency of the lateral compressive strain transferring into the channel region [P1].

2. Dielectric Surface Masking

The gate electrode stack—comprising high-k dielectric layers, metal work-function layers, and polycrystalline silicon—is fully encapsulated by dielectric sidewall spacers (typically composed of silicon nitride and silicon dioxide) [T1]. Shallow trench isolation (STI) oxides surround the active area boundaries [A2]. These oxide and nitride surfaces must remain completely unreactive to silicon and germanium adatoms during epitaxy to prevent amorphous or polycrystalline deposition outside the S/D regions [T2].

3. Surface Termination and Oxide Removal

Chemical vapor deposition (CVD) epitaxy is sensitive to native oxides and atomic-scale surface contaminants [T2]. Prior to entering the epitaxy reaction environment, the exposed silicon surface undergoes dilute hydrofluoric acid wet cleaning followed by an in-situ thermal hydrogen bake or halogen-assisted chemical clean [T2]. This step removes all native silicon dioxide ($SiO_2$), leaving an atomically clean, hydrogen-terminated silicon substrate [T2]. Any residual oxide islands act as nucleation sites for stacking faults or cause complete epitaxy failure (Engineering Practice).

Physical and Chemical Mechanisms

The selective epitaxial growth mechanism in 28nm source-drain integration relies on balancing thermodynamics, surface kinetics, and gas-phase chemical reactions during precursor delivery [T2].

1. Precursor Reaction Chemistry and Gas-Phase Kinetics

SiGe deposition is typically carried out using precursor chemistry consisting of silane ($SiH_4$) or dichlorosilane ($SiH_2Cl_2$), germane ($GeH_4$), hydrogen gas ($H_2$) carrier, and hydrochloric acid ($HCl$) gas as a selective etching agent [T2]. The basic heterogeneous decomposition reactions occurring at the hot single-crystal silicon surface can be expressed as [T2]:

$$SiH_2Cl_{2(g)} \rightleftharpoons Si_{(s)} + 2HCl_{(g)}$$

$$GeH_{4(g)} \rightleftharpoons Ge_{(s)} + 2H_{2(g)}$$

During deposition, gaseous species adsorb onto the clean silicon substrate, diffuse across surface terraces, and incorporate into active lattice kink sites [T2].

2. Kinetics of Selectivity Control

Selectivity between single-crystal silicon and insulating dielectric films (spacers and STI) is maintained by competitive adsorption and etching kinetics [T2]. On dielectric materials such as $SiO_2$ or $Si_3N_4$, adatoms have low binding energy, long incubation times for stable nucleus formation, and high surface mobility [T2].

By injecting $HCl$ gas into the reaction environment, any adatoms or micro-nuclei attempting to deposit on the dielectric surfaces are selectively etched away before forming a continuous film [T2]. On single-crystal silicon, adatoms quickly incorporate into the host lattice, where the etching rate by $HCl$ is significantly lower than the growth rate [T2]. The balance of growth and etching rates determines the process window for defect-free selective epitaxy [T2].

               [ Precursor Gas Phase: SiH2Cl2 + GeH4 + HCl + H2 ]
                                 |
        +------------------------+------------------------+
        |                                                 |
        v                                                 v
[ Exposed Single-Crystal Si ]                     [ Dielectric Surface ]
 (High binding energy)                             (Low binding energy)
        |                                                 |
        v                                                 v
[ Rapid Adatom Incorporation ]                   [ High Rate of HCl Etching ]
        |                                                 |
        v                                                 v
[ Pseudomorphic Crystal Growth ]                   [ Zero Deposition / Clean ]

3 [T2]. Lattice Mismatch Strain Engineering Mechanics

Germanium possesses a larger covalent atomic radius and lattice constant than silicon [T1, A2]. When a dilute alloy of $Si_{1-x}Ge_x$ is grown epitaxially on a rigid silicon substrate, the deposited film is forced to conform laterally to the smaller lattice parameter of the substrate [T1]. This pseudomorphic growth state induces biaxial compressive strain within the SiGe film itself [P1, T1].

Because the SiGe structure is bounded by substrate below and open air above, it relaxes vertically (out-of-plane expansion) while exerting a lateral reaction force against the adjacent channel region [P1, T1]. This mechanism forms the core of PMOS strain engineering SiGe, delivering a longitudinal uniaxial compressive stress ($S_{xx}$) directly under the gate dielectric [P1].

The channel stress magnitude can be expressed qualitatively through elasticity theory as a function of the Ge mole fraction ($x$) and the proximity of the SiGe facet to the channel edge [P1, P3]:

$$\sigma_{channel} \propto E \cdot \varepsilon_{mismatch} \cdot f(\text{geometry}) \quad \text{where} \quad \varepsilon_{mismatch} \propto x_{Ge}$$

4. Crystallographic Faceting and In-Situ Doping

During SiGe deposition, growth kinetics vary across crystal planes [P1]. Growth along the (111) facet is generally slower than along the (100) plane due to differences in surface atom density and bond configuration [P1]. This kinetic anisotropy naturally generates characteristic (111) faceting along the top edges near the spacer wall [P1, P3].

Simultaneously, diborane ($B_2H_6$) is introduced to achieve in-situ p-type doping [T2]. Incorporating boron during epitaxy yields high electrically active acceptor concentrations without needing high-energy ion implantation steps that could damage the crystal lattice or relax the accumulated strain [P2].

Downstream Impact and Failure Propagation

Process variations or kinetic imbalances during selective epitaxy ripple downstream through the 28nm manufacturing module:

+-------------------------------------------------------------------------+
|                    Selective Epitaxy Defect Modes                       |
+-------------------------------------------------------------------------+
       |                                   |                              |
       v                                   v                              v
[ High Ge / Exceeded h_c ]     [ Excess HCl / Low Temp ]      [ Loss of Selectivity ]
       |                                   |                              |
       v                                   v                              v
[ Misfit Dislocations ]            [ Facet Voiding ]             [ Poly-SiGe on Spacers ]
       |                                   |                              |
       v                                   v                              v
[ Complete Strain Relaxation ]     [ High Contact Resistance ]   [ Gate-to-S/D Short Circuit ]
       |                                   |                              |
       v                                   v                              v
[ Degradation of Hole Mobility ]   [ High Series Resistance ]    [ Total Die Yield Loss ]

1 [P1]. Lattice Misfit Dislocations and Strain Relaxation

If the Ge concentration exceeds the critical pseudomorphic limit for a given film volume, the accumulated elastic strain energy exceeds the formation energy of structural dislocations [P3, A2]. The crystal lattice relaxes by generating misfit and thread dislocations [P3, A2]. Strain relaxation destroys the channel compressive stress field, dropping hole mobility back to un-strained silicon levels [P1, P3]. Furthermore, threading dislocations that intersect the reverse-biased source/drain p-n junction act as generation-recombination centers, causing high off-state junction leakage ($I_{off}$) [P2].

2. Loss of Deposition Selectivity

If the partial pressure of $HCl$ is too low or surface contaminants alter adatom kinetics, selective epitaxy degrades [T2]. Amorphous or polycrystalline SiGe nodules nucleate on the silicon nitride spacers [T2]. During subsequent self-aligned silicide processing, these metallic or conductive poly-SiGe residues bridge the gate-to-source or gate-to-drain gap, resulting in short circuits and catastrophic yield loss [A1].

3. Facet Voiding and Contact Resistance Degradation

Imbalanced facet growth rates can create deep structural voids at the interface between the eSiGe fill and the gate sidewall spacer [P1, P3]. Downstream silicidation steps (e (Engineering Practice).g., cobalt or nickel-platinum silicide formation) fail to uniformly wet these sub-surface voids [A1, T3]. This produces high parasitic series resistance ($R_{sd}$) and contact resistance ($R_c$), degrading transistor drive current ($I_{on}$) even if local channel strain remains high [T3].

Walk the Real Step

To explore where this selective deposition operation sits within the interactive manufacturing sequence, view the full module integration context in the software environment:

• Open SD Step 100 in the interactive flow

In Step 100 of the 28nm source-drain module, selective epitaxy transforms the exposed crystalline cavities into operational strain sources [A1]. Operating in a chemical vapor deposition environment, the process balances gas delivery, thermal conditions, and selectivity controls to grow heavily boron-doped SiGe S/D structures without nucleating unwanted poly-silicon-germanium on nearby oxide or nitride regions [T2].

Related Learning Paths

To build a complete understanding of front-end and middle-of-line integration within the 28nm Planar Flow, consider these related process flows and engineering analyses:

• 28nm Planar process flow: A comprehensive overview of high-k/metal gate (HKMG) integration, well formation, halo/extension implants, and back-end-of-line handoffs [P1].
• 28nm Planar source-drain integration process flow: A detailed breakdown of cavity etching, surface preparation, selective SiGe epitaxy, and contact silicidation modules [A1].

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