Selective eSi Growth is a source/drain material-growth operation. In the SemiFlows 7nm teaching sequence, eSi Growth — Step 136 follows eSi Spacer and Cavity Etch — Step 134 and Post Etch Clean — Step 135. It supplies a material and geometry handoff; the operation name alone does not establish a dopant recipe, a strain benefit or a completed low-resistance contact.
Start with the exposed growth surface
Exposed crystalline silicon supplies the lattice template for epitaxy. The surrounding dielectric boundaries help define where growth is intended; a spacer is an exclusion boundary, not the crystal template. Surface preparation and contamination can change nucleation and crystalline continuity .
Compare the exposed semiconductor surface with the regions that should remain clear. The existing cavity shape and later growth morphology must fit the surrounding structures. These checks concern the material produced by this operation, rather than a guaranteed device improvement.
Process checkpoint
Understand eSi Growth in context
Compare Step 136 growth surfaces and the downstream handoff; keep activation, strain and contact conditions separate.
Process context for “Selective eSi Source-Drain Growth at 7nm: Material Handoff, Doping and Contact Conditions”: 7nm FinFET · SD · Step 136
Explore Chapter 3 in the foundation guideFollow growth and selectivity separately
In vapor-phase epitaxy, surface reactions provide species that adsorb, move and become incorporated into the growing crystal. Different reaction and nucleation behavior on semiconductor and dielectric surfaces can enable selective growth . In deposition/etch approaches, growth and removal compete. A published high-P Si:P source/drain study reports selectivity and integration choices for its own process; it does not establish perfect selectivity for every eSi operation .
Inspect unwanted nucleation, faceting and the profile presented to the next operation. Successful growth on an intended surface does not prove that every dielectric region remains clear or that neighboring material is electrically isolated.
Distinguish dopant incorporation from activation
When dopants are introduced during growth, total chemical incorporation and the electrically active fraction are different quantities. The high-P Si:P study discusses phosphorus-vacancy complexes and the consequences of high phosphorus incorporation for its specific layers and integration . It supports treating activation as a separate question, rather than declaring every eSi layer fully activated.
Active carriers, mobility and geometry contribute to conduction within the semiconductor. Sheet resistance also depends on the conducting thickness . Changing total dopant incorporation alone does not establish how those quantities change in the current teaching Step.
Keep contact transport separate from material resistance
A metal–semiconductor contact is formed later. Its specific contact resistivity depends on interface and carrier conditions. Higher active carrier concentration can enhance tunneling under suitable barrier conditions, but this interface mechanism is different from semiconductor sheet resistance .
Vohra and colleagues compare phosphorus activation and contact behavior in several epitaxial materials for Ge nMOS devices, including Si:P. Their results depend on the material stack and process compatibility . That comparison is a conditional literature example, not a measurement of Step 136 or a guarantee for this 7nm teaching flow.
Keep material resistance, specific contact resistivity and total contact resistance distinct. Contact dimensions, interface chemistry and current spreading also affect the later result. Epitaxy completion does not mean that the contact has already formed.
Treat strain as a material-system question
The present Flow has a separate eSiGe Growth operation. A silicon–germanium stressor explanation cannot establish that eSi Growth deposits SiGe. The Si:P study examines strain alongside electrical properties for its own material system ; its outcome must not be assigned to a Step merely because the Step is named epitaxy.
Strain transfer depends on the actual composition, geometry, constraints and relaxation. For Step 136, verify what material and shape are created, and keep any proposed strain benefit conditional on evidence for that material system.
Trace the actual downstream handoff
Step 136 is followed by Post Epi Rinse — Step 137 and the protection-spacer operations. The immediate handoff is grown material and a surface/profile for later processing, rather than an already completed contact.
Useful questions for the interactive Step are:
- Which exposed crystal regions receive the intended growth?
- Are there unwanted deposits in the dielectric exclusion regions?
- How do facets and pattern-dependent growth affect the downstream surface?
- If doping or strain is relevant, which conditions and evidence establish activation or stress transfer?
- Which electrical and interface outcomes must later operations still establish?
Walk the real Step
Use the Step to compare the upstream cavity/cleaning state, the grown structure and the downstream handoff. The link opens the existing 7nm reading route; full text follows your current account access. Use the Step for principles and integration handoffs.
Frequently asked questions
What does selective eSi Growth do in this teaching flow?
It adds semiconductor material at the intended source/drain growth surfaces and supplies a material/profile handoff. It does not, by itself, specify a dopant recipe or guarantee activation, strain or contact performance.
Does silicon epitaxy always create beneficial tensile strain?
No. A strain benefit depends on the material system, geometry, constraints and relaxation. The separate eSiGe operation does not prove a particular strain result for eSi Growth.
Is lower sheet resistance the same as improved contact transport?
No. Sheet resistance describes conduction in a semiconductor layer; a later metal–semiconductor contact has additional interface and barrier conditions. Higher total dopant incorporation alone does not guarantee improvement in either quantity.
References
(Invited) Selective Epitaxial Growth of High-P Si:P for Source/Drain Formation in Advanced Si nFETs
E. Rosseel, S. Dhayalan, A. Hikavyy, R. Loo, H. Profijt, D. Kohen et al.
Source/Drain Materials for Ge nMOS Devices: Phosphorus Activation in Epitaxial Si, Ge, Ge1−x Sn x and Si y Ge1−x−y Sn x
A. Vohra, I. Makkonen, G. Pourtois, J. Slotte, C. Porret, E. Rosseel et al.
Silicon VLSI Technology - Full
James D. Plummer, Michael D. Deal, Peter B. Griffin
Silicon VLSI Technology · ISBN 978-0130850379