Function in the Complete Flow
In sub-10nm logic manufacturing, the integration of selective epitaxial silicon (eSi) in the source and drain regions of n-channel Field-Effect Transistors (nFETs) represents a core module within the 7nm FinFET process flow . This single module receives three-dimensional silicon fins that have been recessed following gate spacer formation, surrounded by dielectric insulation materials and sacrificial dummy gate structures . The primary task of this step is to selectively grow single-crystal silicon with heavy in-situ n-type dopant (e.g., phosphorus) incorporation inside the recessed active source and drain areas while maintaining complete selectivity over surrounding dielectric surfaces .
Once completed, the selective epitaxy module hands off a raised, strain-engineered, and heavily doped source-drain structure to downstream process steps , . These downstream operations include post-epitaxy cleaning, dielectric ILD0 (interlayer dielectric zero) gap-fill deposition, sacrificial dummy gate removal for high-k metal gate (HKMG) insertion, and self-aligned contact silicidation , . Without the precise execution of this raised source-drain (RSD) structural buildup, advanced Fin Field-Effect Transistors (FinFETs) at the 7nm node would suffer from extreme parasitic resistance, unmanageable short-channel effects, and severe contact silicide encroachment into the thin conduction channel , .
[Upstream Recessed Fins & Spacers]
│
▼
┌──────────────────────────────────────────┐
│ Selective eSi Source-Drain Growth Step │
│ - Chemical Vapor Deposition Selectivity │
│ - In-Situ Phosphorus Doping │
│ - Pseudomorphic Lattice Strain Tuning │
└──────────────────────────────────────────┘
│
▼
[Downstream Gate-Last HKMG & Contact Silicidation]
Guided route
eSi Growth
This article maps to Chapter 3 (Source/drain) of the 7nm FinFET structural spine — 6 stops through the complete flow, each with rationale and 2.5D cross-section evolution.
- 1Active region
- 2Gate coordinates
- 3Source/drainThis article
- 4Final gate
- 5Contacts
- 6Back-end handoff
Upstream Input State
The structural and chemical condition of the wafer entering the selective eSi source-drain step dictates the quality of the resulting single-crystal film . Prior to selective growth, upstream etch modules recess the exposed single-crystal silicon fins to a target depth below the original top surface of the fin . The sidewalls of the gate structures are fully encapsulated by dielectric spacers, typically composed of low-k oxide or silicon nitride compounds, which prevent epitaxy from contacting the sacrificial dummy gate .
At the atomic level, the recess process leaves the exposed silicon surface vulnerable to atmospheric oxidation, fluorocarbon residues from reactive ion etching, and lattice displacement damage . Consequently, an in-situ clean—often utilizing gas-phase chemical etching or elevated thermal baking—is executed immediately prior to epitaxy to remove native silicon oxide and atomic contaminants (Engineering Practice). Achieving an atomistically clean, hydrogen-passivated crystalline silicon template is essential; any residual oxide or interfacial contamination inhibits crystallographic alignment, causing defect nucleation, stacking faults, or polycrystalline growth during epitaxy .
Physical and Chemical Mechanisms
Reaction Kinetics and Chemical Selectivity
Selective epitaxial growth (SEG) of eSi relies on chemical vapor deposition (CVD) processes that operate in a delicate kinetic regime where silicon deposition occurs rapidly on single-crystal silicon, but is completely suppressed on dielectric surfaces like silicon dioxide or silicon nitride , . This selective window is achieved by balancing silicon-bearing precursor gases (such as chlorosilanes or silane derivatives) with chlorine-based etchant species (Engineering Practice).
On single-crystal silicon surfaces, precursor molecules chemisorb and dissociate into mobile adatoms, which migrate across the surface to incorporate into atomic step edges, maintaining the underlying crystal lattice template . Conversely, on amorphous dielectric spacers, adatom nucleation requires overcoming a high thermodynamic energy barrier (Engineering Practice). Chlorine species preferentially attack and etch weakly bound silicon adatoms on dielectric surfaces before stable nuclei can form, thereby guaranteeing zero deposition on sidewall spacers while permitting single-crystal growth on the fin recesses , .
Dielectric Spacer Surface: Single-Crystal Silicon Fin:
Etchant Species (Cl) Precursor Adatoms (Si, P)
│ │
▼ ▼
[Weak Adatom Nucleation] [Lattice Step-Edge Incorporation]
│ │
▼ ▼
(Desorption / Etched) (Pseudomorphic Single-Crystal Growth)
Band Structure Engineering and Carrier Tunneling Physics
At the 7nm node, the physical area available for source-drain metal contacts is drastically scaled down , . According to quantum tunneling theory, the specific contact resistivity at a metal-semiconductor interface is exponentially dependent on the Schottky barrier width, which scales inversely with the square root of the active dopant concentration .
To minimize contact resistance, the eSi layer is heavily doped in-situ with phosphorus atoms . High phosphorus incorporation shifts the local Fermi level toward the conduction band edge and significantly narrows the space-charge depletion region at the contact surface , . This structural modification enables high-probability carrier tunneling through the Schottky barrier rather than relying on thermal emission over it, dramatically lowering contact resistance .
$$\rho_c \propto \exp\left( \frac{\sqrt{\epsilon m^*} \Phi_B}{\hbar \sqrt{N_D}} \right)$$
where $\Phi_B$ is the effective barrier height, $N_D$ is the active dopant concentration, $m^*$ is the carrier effective mass, and $\epsilon$ is the semiconductor permittivity , .
Strain Physics and Defect Thermodynamics
Substitutional incorporation of phosphorus atoms into the single-crystal silicon lattice plays a dual role: it modulates electrical conductivity and induces mechanical stress . Because the covalent radius of a phosphorus atom is smaller than that of a silicon atom, substituting silicon lattice sites with phosphorus introduces pseudomorphic tensile strain into the eSi structure . When grown on nFET source-drain regions, this tensile strain transfers into the adjacent silicon channel region , .
Tensile stress alters the crystal lattice symmetry, breaking the six-fold degeneracy of the silicon conduction band valleys , . It lowers the two-fold degenerate transverse valleys relative to the four-fold degenerate longitudinal valleys, reducing intra-valley carrier scattering and decreasing the in-plane electron effective mass , . This physical transformation directly boosts electron mobility within the nFET channel, enhancing device drive current , .
However, high chemical phosphorus concentrations introduce severe point-defect dynamics . Above certain equilibrium thresholds, excess phosphorus atoms combine with lattice vacancies to form inactive phosphorus-vacancy clusters . These complexes do not contribute free electrons to conduction and can relax compressive/tensile strain . Advanced millisecond annealing steps (such as laser or flash annealing) are integrated downstream to dissociate these complexes, driving phosphorus into active substitutional lattice sites without causing excessive dopant diffusion into the channel , .
Downstream Impact and Failure Propagation
The execution of the selective eSi step directly influences downstream module yield and transistor electrical performance , . The interplay between process variations in this step and device failure modes highlights the tight coupling within the 7nm FinFET source-drain integration process flow .
Epi Profile Tradeoff Spectrum:
Under-Growth Optimal Target Over-Growth
┌──────────────┐ ┌──────────────┐ ┌──────────────┐
│ High Series │ ◄───────────► │ Low Res, │ ◄───────────► │ Epi Merging, │
│ Resistance, │ │ Controlled │ │ Gate Shorts, │
│ Silicide │ │ SCE/DIBL │ │ High Parasitic│
│ Encroach │ │ │ │ Capacitance │
└──────────────┘ └──────────────┘ └──────────────┘
Height and Volumetric Profiles
- Under-growth (Insufficient Epitaxial Volume): If the selective eSi growth rate is insufficient or halted prematurely, the raised source-drain structure will fail to achieve the required height above the fin recess . Downstream silicide metallization will then consume silicon too close to the sensitive channel extension region, leading to silicide encroachment, junction leakage, and elevated parasitic series resistance , .
- Over-growth and Merging: Excessive eSi growth causes adjacent epitaxy facets to expand laterally and merge uncontrollably across adjacent fins . Unintended structural merging increases parasitic gate-to-source/drain fringe capacitance, degrading high-frequency circuit performance , . In extreme cases, over-grown eSi spills over dielectric spacers, causing direct electrical short circuits to the gate electrode during replacement metal gate processing , .
Faceting and Abruptness Tradeoffs
Epitaxial growth on three-dimensional fins exhibits anisotropic growth rates along different crystallographic planes (such as ${100}$ versus ${111}$ planes) (Engineering Practice). Uncontrolled faceting leads to non-uniform current density distributions at the contact interface and irregular lateral dopant transitions . If the lateral transition of phosphorus dopants under the gate spacer is insufficiently abrupt, the effective channel length shrinks unpredictably, exacerbating short-channel effects (SCE) and drain-induced barrier lowering (DIBL) . Conversely, if the dopant profile is overly abrupt or set too far back from the channel edge, extension resistance increases, limiting drive current , .
Walk the Real Step
To explore where this specific step resides within the complete 7nm manufacturing module, inspect the detailed process sequencing in our interactive step view (Engineering Practice).
Open SD Step 136 in the interactive flow
This interactive step highlights the position of the selective eSi deposition relative to upstream fin recessing and downstream contact silicidation steps within the overall integration flow .
Related Learning Paths
Understanding selective eSi source-drain growth requires familiarization with several closely adjacent semiconductor modules:
- P-Type Source-Drain Epitaxy (eSiGe): While nFETs utilize eSi with phosphorus doping for tensile strain, p-channel Field-Effect Transistors (pFETs) utilize silicon-germanium (eSiGe) with boron doping to introduce compressive strain into the channel, enhancing hole mobility , .
- Contact Silicidation and Interface Engineering: Following source-drain epitaxy, transition metals (such as titanium or cobalt) are deposited and reacted with the eSi layer to form low-resistance silicide contacts, requiring precise control over silicide encroachment , .
- Replacement Metal Gate (RMG) Modules: The high-thermal-budget epitaxy step must take place while sacrificial dummy gates are still present, insulating the high-k dielectric and work-function metal stacks from severe thermal degradation , .
Future Outlook
As device architectures scale beyond 7nm FinFETs into gate-all-around (GAA) nanosheet structures and complementary field-effect transistors (CFETs), selective source-drain epitaxy faces unprecedented geometric constraints . In nanosheet devices, eSi must be selectively grown in the narrow spaces between stacked sheet channels while avoiding unwanted growth on inner dielectric spacers .
Furthermore, solid solubility limits of phosphorus in silicon motivate the exploration of novel cryogenic implantation combined with rapid thermal annealing or non-equilibrium atomic layer epitaxy (ALE) techniques to achieve ultra-high dopant activation without defect clustering , . These developments ensure that selective epitaxy principles remain foundational to next-generation logic technologies (Engineering Practice).