“Leakage” describes an unwanted current, not a unique physical mechanism. Isolation-related leakage concerns paths that defeat the intended separation of device regions. Junction leakage concerns transport associated with a biased semiconductor junction. A defect near isolation can influence junction leakage, so the categories can overlap rather than form mutually exclusive boxes.
Identify the terminals and the boundary
Before assigning a name, ask between which terminals current is measured and what barrier was intended to limit it. Current flowing along a surface between adjacent regions is a different hypothesis from current generated in the depletion region of a reverse-biased junction.
A test structure can include several paths simultaneously. The measured current is their combined outcome under the applied conditions. Naming the nearest visible structure does not prove which path dominates.
Process map
A selected 2-step learning trail in 28nm Planar Flow
Examine the silicon and oxide interface formed along an isolation trench.
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A junction has several possible leakage contributions
Thermal generation in a depleted region, carrier diffusion from neighboring regions, and field-assisted transport can contribute under different conditions. Defects and interfaces can alter those contributions. The relative importance depends on the junction, its environment and bias.
Consequently, “junction leakage” does not automatically mean a bulk-crystal problem. A junction near a damaged sidewall can have a significant interface-related contribution, even though the electrical measurement is still described as junction leakage.
| Candidate path | Boundary to examine | Important qualification |
|---|---|---|
| Near-surface conduction between regions | Surface potential and isolation geometry | An intact-looking dielectric does not prove electrical isolation |
| Generation near a junction | Depletion region and relevant defects | Surface and bulk contributions can coexist |
| Field-assisted junction transport | Local field and band structure | Bias dependence alone is not a unique fingerprint |
| Conductive residue or bridge | Physical continuity between terminals | This is not established merely by seeing an empty dielectric cavity |
Geometry and interface quality must be read together
An isolation trench can interrupt a geometric route while introducing a sidewall interface. If that interface has unfavorable electrical behavior, a different unwanted current can remain or appear. The correct question is therefore not just whether dielectric occupies the trench, but whether the completed structure blocks the relevant current path.
Conversely, reducing junction-related generation does not certify isolation between every neighboring region. The two objectives require appropriately targeted evidence.
A practical reasoning example without a recipe
Imagine two structures with similar trench outlines but different unwanted current. The drawing alone cannot decide between interface condition, junction profile or another path. Now imagine current changes when an isolation geometry changes. That correlation motivates a hypothesis, but the modification may also have changed sidewall area or local electrostatics.
A careful explanation states the proposed path and acknowledges those coupled changes. It avoids declaring a single root cause from one visual defect or one current value.
Source links
References
Physics of Semiconductor Devices - Full
S. M. Sze, Kwok K. Ng
Physics of Semiconductor Devices · ISBN 978-0-471-14323-9