7nm Dummy Gate Etch Over Fins: Physical Mechanisms, Integration Logic, and Downstream Reliability

Function in the Complete Flow

In 7nm Fin-shaped Field-Effect Transistor (FinFET) logic manufacturing using a replacement metal gate (RMG) scheme, dummy gate patterning is a foundational front-end-of-line (FEOL) module. Rather than forming the final functional metal gate stack directly during initial front-end processing, a sacrificial amorphous silicon (a-Si) structure is defined first to act as a temporary physical template.

The primary objective of the amorphous silicon (a-Si) dummy gate etch module is to pattern the blanket a-Si film into highly anisotropic, freestanding gate lines running orthogonally across three-dimensional silicon fins. Positioned after hardmask definition and surface cleaning, this step transfers the lithographically defined critical dimension (CD) into the dummy gate material with minimal line-edge roughness (LER) and vertical profile distortion. Because the dummy gate directly establishes the physical template for the gate length ($L_g$), its geometry and fidelity are paramount.

+---------------------------------------------------------------------------------+
|                              UPSTREAM INPUT STATE                               |
|   - Vertical crystalline Si fins protruding above Shallow Trench Isolation (STI)|
|   - Thin protective gate oxide / sacrificial oxide skin over fin channels       |
|   - Continuous / blanket amorphous silicon (a-Si) sacrificial layer             |
|   - Patterned hardmask lines lines defining gate critical dimension           |
+---------------------------------------------------------------------------------+
                                        |
                                        v
+---------------------------------------------------------------------------------+
|                     DUMMY GATE PATTERNING ETCH (STEP 117)                       |
|   - Directional dry plasma etch transferring hardmask pattern into a-Si core    |
|   - Synergistic ion-radical halogen reactions forming volatile silicon halides  |
|   - Selective over-etch stopping on thin protective oxide skin                  |
+---------------------------------------------------------------------------------+
                                        |
                                        v
+---------------------------------------------------------------------------------+
|                              DOWNSTREAM HANDOFF                                 |
|   - Freestanding a-Si dummy gate lines orthogonal to 3D active fins             |
|   - Intact thin protective oxide layer preserving fin channel surface           |
|   - Prepared state for dielectric spacer deposition & source/drain engineering   |
+---------------------------------------------------------------------------------+

The resulting freestanding a-Si gate structure serves as a mechanical and chemical placeholder. It protects the underlying protective interfacial oxide and active fin channel during subsequent high-temperature operations, including sidewall spacer formation, halo/extension implants, and selective raised source/drain epitaxy. The dummy gate etch must achieve high material selectivity relative to the underlying protective oxide skin and STI dielectric while maintaining a straight vertical profile across dense and isolated fin arrays.

To understand how this critical step interfaces with surrounding front-end-of-line modules, explore the broader 7nm FinFET process flow documentation.

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Upstream Input State

Prior to the dummy gate etching step, the wafer undergoes active area definition, fin patterning, shallow trench isolation recessing, interfacial oxide formation, dummy material deposition, and hardmask patterning. Diagnosing dry etch profile evolution requires an understanding of these incoming physical boundary conditions.

                     [Patterned Composite Hardmask]
                        +------------------------+
                        |   hardmask lines     |
+-----------------------+------------------------+-----------------------+
|                                                                        |
|                  Sacrificial Amorphous Silicon (a-Si)                  |
|                                                                        |
+-----------------------+------------------------+-----------------------+
|      STI Oxide        | Thin Protective Oxide  |       STI Oxide       |
+-----------------------+------------------------+-----------------------+
|     Crystalline Si    |   Active Silicon Fin   |     Crystalline Si    |
|      Substrate        +------------------------+      Substrate        |
+------------------------------------------------------------------------+

The incoming structural matrix consists of the following features:

• Active Silicon Fins: High-aspect-ratio vertical crystalline silicon channels protruding above the recessed STI oxide field. The fins exhibit smooth, slightly tapered vertical sidewalls and rounded top corners.
• Protective Interfacial Oxide: An ultra-thin thermally grown or chemically formed oxide skin coating the top and sidewalls of the active silicon fins. This layer acts as a vital etch stop, protecting the crystalline silicon channel from direct ion impact.
• Sacrificial Amorphous Silicon Layer: A continuous, conformal or planarized a-Si film covering the 3D fin topography, filling the gaps between fins and establishing the height of the sacrificial gate structure.
• Composite Hardmask Pattern: Lithographically defined hardmask lines (composed of silicon nitride, silicon oxynitride, or oxide multi-patterning stacks) positioned on top of the a-Si layer, defining the line-space grating and lateral gate length ($L_g$).

At this junction, the dry etch must clear the a-Si material down to the narrow spaces between 3D fins without carving into the STI surface or breaching the thin protective oxide skin.

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Physical and Chemical Mechanisms

Etching an amorphous silicon dummy gate over complex three-dimensional topography requires balancing chemical reaction kinetics with directional ion transport to achieve profile verticality and surface selectivity.

+---------------------------------------------------------------------------------+
|                      PLASMA REACTOR (ICP / SYNCHRONOUS PULSED)                  |
|                                                                                 |
|   Ion Acceleration Phase:                                                       |
|   - Direct energy transfer breaks Si-Si surface bonds                           |
|   - Directional sheath field drives HBr+ / Cl+ ions vertically                  |
|                                                                                 |
|   Radical Reaction Phase:                                                       |
|   - Neutral Br* / Cl* radicals adsorb on activated silicon sites                |
|   - Desorption of volatile reaction products: SiBr4(gas), SiCl4(gas)             |
+---------------------------------------------------------------------------------+
                                        |
                                        v
+---------------------------------------------------------------------------------+
|                         SURFACE REACTION MECHANISM                              |
|                                                                                 |
|   1. Halogen adsorption:  Si(solid) + xBr* -> SiBr_x(adsorbed)                  |
|   2. Volatile desorption: SiBr_x(adsorbed) + ion energy -> SiBr4(gas)^          |
|   3. Oxide Protection:    Trace O2 forms SiO2 skin on oxide surfaces,           |
|                           suppressing oxide removal rate                        |
+---------------------------------------------------------------------------------+

Dry Etch Plasma Chemistry and Volatile Byproducts

Dummy gate dry etching is performed in inductively coupled plasma (ICP) reactors using halogen-based chemistries, primarily hydrogen bromide (HBr), chlorine (Cl2), and oxygen (O2), diluted with helium or argon. Etching proceeds via a radical-ion synergistic mechanism:

$$\text{Si (solid)} + 4\text{Br}^* \rightarrow \text{SiBr}_4 (\text{gas})\uparrow$$

$$\text{Si (solid)} + 4\text{Cl}^* \rightarrow \text{SiCl}_4 (\text{gas})\uparrow$$

Neutral halogen radicals adsorb onto dangling silicon bonds, weakening the underlying Si-Si back-bonds. Low-energy ions accelerated across the plasma sheath supply localized momentum to desorb volatile silicon tetrahalide byproducts (SiBr4, SiCl4). Chemical reactions can be very selective whereas physical processes like sputtering tend to be similar for most materials [T1].

Selectivity to the underlying thin oxide skin is governed by bond dissociation energies; the Si-O bond is significantly stronger than the Si-Si bond. Introducing trace oxygen into the halogen gas mixture generates reactive oxygen species ($O^*$) that passivate exposed oxide surfaces by forming a thin silicon-oxychloride/oxybromide passivation layer, suppressing oxide loss:

$$\text{Si} + \text{O}_2^* \rightarrow \text{SiO}_2 (\text{passivation layer})$$

Ion-Radical Balance and Anisotropy Control

Anisotropy is achieved because positive ions ($HBr^+$, $Cl^+$) are accelerated vertically normal to the wafer surface by the sheath electric field, continuously removing sidewall passivation on horizontal surface planes. In contrast, neutral radicals arrive isotropically. To prevent lateral undercut of the a-Si dummy gate sidewalls, passivation-forming chemistries create a protective coating along the vertical a-Si sidewalls.

Excessive ion energy, however, can cause physical sputtering, physical amorphization, and subsurface damage. In advanced nodes, synchronous pulsed plasma technology is employed to modulate source and bias RF power:

1. Power-ON Phase: High electron temperatures dissociate halogen gas into reactive neutral radicals and positive ions, driving directional etching.
2. Power-OFF Phase: Electron temperature cools rapidly, quenching high-energy ion bombardment while allowing neutral radicals to diffuse into high-aspect-ratio spaces, maintaining etch rate uniformity with minimal ion damage.

Multi-Step Etch Sequence and Micro-Loading

Etching a-Si over 3D fin arrays introduces aspect-ratio-dependent etching (ARDE) and micro-loading. Open field areas etch faster than dense fin arrays due to radical depletion in narrow spaces. To achieve uniform clearing without damaging underlying structures, a multi-step etch process is used:

• Main Etch (ME): High anisotropic etch rate chemistry optimized to rapidly remove the bulk of the upper a-Si layer, establishing straight dummy gate sidewalls.
• Soft Over-Etch (OE): Low ion bias, highly selective pulsed-plasma chemistry designed to clear a-Si remnants residing in the tight recessed corners between 3D fins and STI fields, stopping on the thin protective oxide layer.

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Downstream Impact and Failure Propagation

Defects or profile non-uniformities introduced during the a-Si dummy gate etch directly degrade downstream spacer formation, source/drain junction engineering, and replacement gate integration.

+-----------------------------------------------------------------------------------+
|                        DUMMY GATE ETCH FAILURE MODES                              |
+-----------------------------------------------------------------------------------+
           |                                 |                                 |
           v                                 v                                 v
+-----------------------+         +-----------------------+         +-----------------------+
|   a-Si FOOTING /      |         |   PROFILE Taper /     |         |   OXIDE BREACH /      |
|   RESIDUAL BRIDGING   |         |   CD LOSS / LER       |         |   FIN TOP FACETING    |
+-----------------------+         +-----------------------+         +-----------------------+
           |                                 |                                 |
           v                                 v                                 v
+-----------------------+         +-----------------------+         +-----------------------+
| - Spacer Profile      |         | - Effective Lg Shift  |         | - Channel Si Loss     |
|   Distortion          |         | - Vt Spread / Variance|         | - Elevated Dit / SS   |
| - Gate-to-Gate Shorts |         | - Ion / Ioff Shift    |         | - Gate Oxide Breakdown|
| - Epi Cavity Blocking |         |                       |         |                       |
+-----------------------+         +-----------------------+         +-----------------------+

Oxide Breach and Active Fin Erosion

If the dry etch exhibits excessive ion energy or insufficient oxygen self-passivation during the over-etch step, energetic ions break through the thin protective oxide skin.

• Physical Result: Sputtering and faceting of the crystalline silicon fin, particularly at vulnerable top corners.
• Electrical Impact: Plasma-induced charging and energetic ion bombardment can damage interfacial dielectric bonds, increasing gate leakage and degrading overall device reliability [P5]. Plasma charging and physical ion impact create interface traps ($D_{it}$) and fixed charge, degrading subthreshold swing ($SS$) and carrier mobility ($mu_{ns}$):

$$I_{ds} = \frac{W}{L} Q_{inv} \mu_{ns} V_{ds}$$

Loss of fin silicon reduces effective channel width ($W_{eff}$), directly suppressing drive current ($I_{on}$) and increasing threshold voltage ($V_{th}$) variability across the wafer.

In inversion, increased surface roughness scattering significantly degrades carrier mobility ($mu_{ns}$), directly limiting transistor switching speed. Furthermore, damaged interface quality increases off-state leakage current ($I_{off}$), violating strict static power budgets in mobile platforms:

$$I_{ds} \propto \exp\left(\frac{q V_{gs}}{\eta k T}\right)$$

Profile Distortion, Footing, and Undercut

Non-ideal ion-radical balance causes profile distortions such as footing at the gate base or isotropic undercutting beneath the hardmask.

• Physical Result: Footing leaves residual a-Si filaments in the narrow spaces between fins, while profile tapering widens the gate base.
• Electrical Impact: Sidewall spacers deposited over footed gate profiles inherit asymmetric, distorted geometries. This disrupts subsequent halo/extension ion implantation profiles, shifting target channel length ($L_g$) and degrading short-channel control ($DIBL$). Severe footing can cause gate-to-gate bridging shorts or block selective epitaxy in source/drain regions.

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Walk the Real Step

To see how this a-Si dummy gate etch module is integrated into the full 7nm manufacturing baseline, explore the interactive process flow step:

• Etch a-Si Gate

This step captures the operational transition where the blanket a-Si film is patterned over 3D active fin structures prior to spacer formation. It demonstrates how anisotropic plasma chemistry, selectivity controls, and surface passivation operate to establish precise sacrificial gate lines.

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Related Learning Paths

To further deepen your understanding of 7nm logic integration, review these closely related technical articles:

• Explore the foundational architecture and complete module sequence in the 7nm FinFET process flow.
• Examine the downstream replacement metal gate, work-function tuning, and metal fill mechanisms in the 7nm FinFET gate stack integration process flow.

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Future Outlook

As logic scaling transitions beyond FinFETs into sub-3nm Gate-All-Around (GAA) nanosheet architectures, dummy gate etching faces structural and material evolution.

       7nm FinFET Architecture                 Sub-3nm Gate-All-Around (GAA) Nanosheet
+-----------------------------------+     +-----------------------------------------------+
|    Bulk a-Si Gate Over 3D Fins    |     |   a-Si Gate Over Si/SiGe Superlattice Stack   |
| (Selective to Protective Ox Skin) |     | (Selective to Exposed Si and SiGe Sheet Edges)|
+-----------------------------------+     +-----------------------------------------------+
                  |                                               |
                  v                                               v
+-----------------------------------+     +-----------------------------------------------+
| Vertically Directional Plasma RIE |     | Atomic Layer Etching (ALE) / Cryo Plasma RIE  |
| Halogen Radicals + Bias Pulsing   |     | Monolayer Precision, Zero Sputter Damage      |
+-----------------------------------+     +-----------------------------------------------+

1. GAA Nanosheet Gate Patterning: In nanosheet architectures, the dummy gate dry etch must pattern a-Si over an alternating silicon/silicon-germanium (Si/SiGe) superlattice stack. Etching must stop cleanly on ultra-thin protective layers without eroding exposed SiGe sheet edges.
2. Atomic Layer Etching (ALE): To eliminate physical sputtering damage and achieve sub-nanometer critical dimension control, dry etching is transitioning toward atomic layer etching (ALE). Thermal and plasma-assisted ALE steps utilize sequential, self-limiting surface reaction cycles (such as localized chlorination/fluorination followed by ligand exchange), removing target material monolayer by monolayer without inducing lattice defects.
3. Cryogenic Etching: Lowering wafer stage temperatures down to cryogenic regimes alters radical adsorption kinetics. Surface reaction rates on vertical sidewalls are strongly suppressed, enabling high vertical directionality and extreme selectivity to underlying ultra-thin dielectrics at ultralow ion energies.