Function in the Complete Flow
In sub-10nm logic manufacturing, the replacement metal gate (RMG) scheme—often referred to as the gate-last integration flow—has completely supplanted traditional gate-first approaches . Within the 7nm Fin-shaped Field-Effect Transistor (FinFET) architecture, the removal of the sacrificial template represents a critical turning point where temporary front-end structures give way to functional high-k metal gate (HKMG) stacks .
The primary task of the amorphous silicon (a-Si) gate etch FinFET module is to selectively evacuate the dummy gate electrode material (typically a-Si or polycrystalline silicon) from high-aspect-ratio narrow cavities without damaging the underlying single-crystal silicon channels or the surrounding dielectric spacers , . This step receives a fully planarized dielectric architecture, cleans out the sacrificial gate core across complex three-dimensional topography, and hands off pristine, highly selective open gate trenches ready for interfacial layer optimization, work-function metal deposition, and fill metal chemical mechanical planarization (CMP) , .
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| UPSTREAM INPUT STATE |
| - Vertical crystalline Si fins over Shallow Trench Isolation (STI) |
| - Sacrificial thin oxide protective skin over active fin channels |
| - Patterned sacrificial a-Si dummy gates with hard masks & SiN spacers |
| - High-temperature-activated raised S/D epitaxy & planarized ILD0 oxide |
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| DUMMY GATE ETCH OVER FINS (STEP 117 FLOW) |
| - Selective chemical oxidation & ion-assisted volatile byproduct removal |
| - Time-modulated pulsed plasma dry etch to prevent fin top faceting |
| - Soft, ultra-high-selectivity wet chemical clean to clear a-Si residues |
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| DOWNSTREAM HANDOFF |
| - Pristine open gate trenches with untouched substrate fin profile |
| - Exposed ultra-thin interfacial oxide template |
| - Conformal RMG stack deposition: HK dielectric + work-function metals |
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Because the active silicon fin channel is separated from the aggressive dry etching environment by only an ultra-thin sacrificial oxide layer, the 7nm dummy gate removal mechanism must exhibit near-infinite etching selectivity of silicon to silicon oxide, as well as silicon to silicon nitride (SiN) sidewall spacers , . Any unintended consumption of the silicon fin alters the effective channel width, degrades short-channel control, and induces severe threshold voltage variations across the die , . Thus, dummy gate removal serves as the structural gateway connecting high-temperature front-end-of-line (FEOL) source/drain processing to low-temperature gate template etch integration .
To understand how this critical step interfaces with surrounding FEOL steps, explore the broader 7nm FinFET process flow documentation .
Guided route
Etch a-Si Gate
This article maps to Chapter 2 (Gate coordinates) of the 7nm FinFET structural spine — 6 stops through the complete flow, each with rationale and 2.5D cross-section evolution.
- 1Active region
- 2Gate coordinatesThis article
- 3Source/drain
- 4Final gate
- 5Contacts
- 6Back-end handoff
Upstream Input State
Prior to entering the dummy gate etch over fins module, the wafer undergoes extensive FEOL patterning, film deposition, thermal annealing, and planarization modules , . Understanding the incoming physical and surface boundary conditions is essential for diagnosing dry etch performance and micro-loading characteristics .
[ILD0 Oxide] [a-Si Dummy Gate] [ILD0 Oxide]
+------------------------+ +------------------------------+ +------------------------+
| | | | | |
| | | | | |
| | | Sacrificial a-Si Core | | |
| | | | | |
+------------------------+ +------------------------------+ +------------------------+
| Low-k Spacer / SiN | | Sacrificial SiO2 Oxide | | Low-k Spacer / SiN |
| (Side) | +------------------------------+ | (Side) |
+------------------------+ | Crystalline Silicon Fin | +------------------------+
+------------------------------+
The incoming structural matrix consists of the following features:
- Active Silicon Fins: High-aspect-ratio vertical crystalline silicon channels protruding from the recessed shallow trench isolation (STI) field oxide , . The fin profile features slight vertical tapering and rounded top corners resulting from self-aligned double patterning (SADP) and reactive ion etching (RIE) modules .
- Sacrificial Interfacial Layer: An ultra-thin thermally grown or chemically deposited silicon dioxide layer coating the top and sidewalls of the active silicon fins , . This sacrificial oxide acts as a chemical and physical etch-stop barrier designed to cushion the crystalline fin from direct ion bombardment during dry etching .
- Sacrificial Dummy Gate Stack: High-aspect-ratio a-Si lines running orthogonal to the underlying silicon fins . This line pattern was originally formed by optical/EUV lithography, hard mask etch, and main dry etch steps, followed by gap fill and CMP to establish a uniform vertical height , .
- Sidewall Spacers: Protective dielectric spacers (typically composed of SiN, silicon oxycarbonitride, or low-k SiBCN films) lining the vertical sidewalls of the dummy gate pattern , . These spacers define the offset distance between the source/drain junction edges and the future replacement gate .
- Raised Source/Drain Epitaxy & ILD0: Heavily doped selective epitaxial structures (such as SiGe for pMOS or SiP/SiC for nMOS) grown on the exposed fin legs adjacent to the spacers , . The entire active area is subsequently buried under a thick first interlayer dielectric (ILD0) oxide layer and planarized via CMP down to expose the bare top surface of the a-Si dummy gate , .
At this junction, the incoming state presents extreme surface topography buried within narrow dielectric trenches . The dummy gate removal process must navigate tight aspect ratios, differential thermal strain, and sensitive interfaces without causing mechanical collapse or chemical damage .
Physical and Chemical Mechanisms
The fundamental physics and chemistry of the 7nm gate stack integration process flow require removing the a-Si dummy gate with ultra-high selectivity over silicon dioxide, silicon nitride, and low-k spacer dielectrics , . Etching an a-Si dummy gate over three-dimensional fin topography introduces complex physical transport and chemical kinetics challenges , .
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| PLASMA REACTOR (ICP / SYNCHRONOUS PULSED) |
| |
| Dissociation Phase (Power ON): |
| - High energy electrons dissociate halogen gas -> Br*, Cl*, F* radicals |
| - Ion generation -> HBr+, Cl+ directional acceleration |
| |
| Recombination Phase (Power OFF): |
| - Electron temperature cools rapidly |
| - Neutral radical flux dominates surface passivation & isotropic chemical etch|
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| SURFACE REACTION MECHANISM |
| |
| 1 [P1]. Halogen adsorption: Si(solid) + xBr* -> SiBr_x(adsorbed) |
| 2 *(Engineering Practice)*. Volatile desorpt: SiBr_x(adsorbed) + ion energy -> SiBr4(gas)^ |
| 3 *(Engineering Practice)*. Oxide Protection: SiO2 skin resists halogen attack due to high Si-O |
| bond energy relative to Si-Si bonds |
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Dry Etch Plasma Chemistry & Volatile Byproduct Generation
The primary dry etching step typically relies on inductively coupled plasma (ICP) tools using halogen-based gas chemistries, predominantly hydrogen bromide (HBr), chlorine (Cl2), and oxygen (O2), combined with inert diluents like helium or argon . The surface chemistry relies on halogen radical adsorption and ion-assisted thermal desorption of volatile silicon tetrahalides:
$$\text{Si} (\text{solid}) + 4\text{Br}^* \rightarrow \text{SiBr}_4 (\text{gas})\uparrow$$
$$\text{Si} (\text{solid}) + 4\text{Cl}^* \rightarrow \text{SiCl}_4 (\text{gas})\uparrow$$
Thermodynamically, halogen atoms adsorb onto the dangling silicon bonds of the a-Si matrix, weakening the underlying Si-Si back-bonds . Direct ion impact from low-energy plasma ions supplies the localized lattice energy needed to desorb the volatile reaction product, SiBr4 or SiCl4, into the gas phase (Engineering Practice).
Selectivity to the underlying thin silicon dioxide interfacial layer is governed by the difference in chemical bond dissociation energies . The Si-O bond strength is significantly higher than the Si-Si bond strength (Engineering Practice). By introducing controlled trace oxygen into the gas flow, exposed silicon oxide surfaces continuously self-passivate via oxidation, whereas bare silicon is rapidly halogenated and desorbed:
$$\text{Si} + \text{O}_2^* \rightarrow \text{SiO}_2 (\text{passivation layer})$$
Time-Modulated Pulsed Plasma Dynamics
In continuous-wave (CW) high-density plasmas, ion flux, ion energy, and radical concentrations are strongly coupled . Under CW conditions, even moderate ion energy directed at three-dimensional fin corners causes physical sputtering and faceting of the thin protective oxide skin, leading to irreversible active fin erosion , .
To solve this issue in the 7nm gate stack integration flow, advanced dry etching employs synchronous pulsed high-density plasmas . Pulsed plasma technology rapidly modulates the source radio-frequency (RF) power and/or bias RF power between high-power ("ON") and low-power ("OFF") states :
- Power-ON Phase: Energetic electrons dissociate halogen precursor molecules into reactive neutral radicals (Br*, Cl*) and generate positive ions . High electron temperatures drive gas-phase ionization and surface bombardment .
- Power-OFF Phase: Thermal electrons cool rapidly, quenching high-energy ion generation . Meanwhile, neutral radicals—which possess significantly longer chemical lifetimes than charged ions—continue to diffuse deep into the narrow dummy gate trenches .
By adjusting the pulse frequency, duty cycle, and phase synchronization between source and bias power, process engineers can decouple ion energy from neutral radical flux . This time modulation allows the isotropic chemical removal of a-Si to proceed with minimal directional ion bombardment, preventing top-fin faceting and maintaining extreme etch selectivity to ultra-thin oxide templates .
Micro-Loading, Charging, and 3D Topography Effects
As the dummy gate etch approaches the bottom of the high-aspect-ratio trench, aspect-ratio-dependent etching (ARDE) and micro-loading become prominent . In narrow feature openings, physical shadow effects reduce the local flux of neutral halogen radicals compared to wide open areas . Furthermore, electron temperature anisotropy causes differential electrostatic charging between conductive silicon fins and insulating ILD0 sidewalls .
To counter these micro-loading effects, the dry etch process operates in multiple distinct phases :
- Main Etch Phase: Optimized for high anisotropic etch rate to rapidly remove the bulk of the upper a-Si dummy gate core .
- Over-Etch Phase: Shifted toward highly selective, soft pulsed-plasma conditions with low ion bias power to safely clear a-Si remnants residing in the tight corners between fin sidewalls and gate spacers without breaching the thin interfacial oxide , .
Two-Step Dry/Wet Clean Integration
Because complete reliance on dry plasma over-etching risks sputtering thin physical layers, advanced 7nm nodes utilize a dual dry-wet dummy gate removal mechanism . The dry plasma etch step removes the bulk (typically the vast majority) of the a-Si dummy gate material, stopping cleanly on the oxide skin over the fin tops , . Subsequently, an ultra-selective wet chemical polish step (utilizing dilute hot ammonium hydroxide, tetramethylammonium hydroxide, or specialized organic bases) clears any residual a-Si footing along the narrow fin-spacer corners . These wet chemistry formulations achieve high chemical selectivity to single-crystal silicon and oxide, ensuring a residue-free trench without crystalline fin loss .
Downstream Impact and Failure Propagation
Because the dummy gate etch directly exposes the active channel region, process non-uniformities or mechanism failures during this step immediately propagate into catastrophic physical defect modes and severe electrical performance degradation , .
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| DUMMY GATE ETCH FAILURE MODES |
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| | |
v v v
+-----------------------+ +-----------------------+ +-----------------------+
| a-Si MICRO-RESIDUE | | FIN TOP FACETING | | OXIDE BREACH / |
| / INCOMPLETE ETCH | | & SILICON LOSS | | SPACER EROSION |
+-----------------------+ +-----------------------+ +-----------------------+
| | |
v v v
+-----------------------+ +-----------------------+ +-----------------------+
| - RMG Metal Voiding | | - Channel Area Loss | | - Direct S/D Short |
| - Gate Line Shorting | | - Vt Shift / Spread | | - Elevated Dit / SS |
| - Severe Lg Variation | | - Degraded Ion / Ioff | | - Gate Oxide Breakdown|
+-----------------------+ +-----------------------+ +-----------------------+
Fin Top Faceting and Active Silicon Loss
If the dry etching plasma exhibits excessive ion bias energy or insufficient oxygen self-passivation, energetic ions break through the ultra-thin interfacial SiO2 skin . This leads to physical sputtering and crystalline silicon fin faceting, particularly at the vulnerable top corners of the fin , .
- Physical Result: The fin cross-sectional area is reduced, and the rectangular fin profile becomes excessively rounded or pinched , .
- Electrical Impact: Silicon fin loss directly degrades drive current ($I_{on}$) by reducing the effective channel conduction width ($W_{eff}$) , . Furthermore, non-uniform fin erosion across the wafer expands threshold voltage ($V_{th}$) distribution, degrading yield in critical SRAM bitcells .
Interfacial Layer Punch-Through and Surface Damage
Direct plasma exposure can breach the ultra-thin sacrificial oxide layer, causing ion-implantation damage and surface roughness on the single-crystal silicon fin channel , .
- Physical Result: High interface state density ($D_{it}$) and physical roughness formation at the channel surface .
- Electrical Impact: Degraded subthreshold swing ($SS$) and increased drain-induced barrier lowering ($DIBL$) . In inversion, increased surface roughness scattering significantly degrades carrier mobility ($\mu_{ns}$), directly limiting transistor switching speed :
$$I_{ds} = \frac{W}{L} Q_{inv} \mu_{ns} V_{ds}$$
According to classical carrier transport physics, any reduction in surface mobility ($\mu_{ns}$) proportionally suppresses linear drain current . Furthermore, damaged interface quality increases off-state leakage current ($I_{off}$), violating strict static power budgets in mobile system-on-chip (SoC) platforms :
$$I_{ds} \propto \exp\left(\frac{q V_{gs}}{\eta k T}\right)$$
Residual Amorphous Silicon and Micro-Loading Footing
If the over-etch or wet chemical clean is under-designed, micro-loading effects leave a-Si residues (footing) trapped in the tight corners between the fin sidewall and the gate spacer .
- Physical Result: Narrow filaments of conductive a-Si remain in the bottom of the open gate trench .
- Electrical Impact: During subsequent replacement high-k metal gate deposition, the residual silicon prevents conformal work-function metal lining, resulting in local gate voids, work-function shifts, or severe gate-to-channel short circuits .
Spacer Erosion and Gate-to-Drain Shorting
Over-aggressive chemical etching can erode the upper or lower regions of the dielectric sidewall spacers , .
- Physical Result: Thinning or punch-through of the SiN/low-k spacer wall separating the gate trench from the adjacent raised source/drain epitaxy , .
- Electrical Impact: High gate-to-source/drain leakage, degraded parasitic capacitance integrity, and immediate catastrophic dielectric breakdown between the work-function metals and the heavily doped epitaxy , .
Walk the Real Step
To see how this dummy gate etch module is integrated into the full 7nm manufacturing baseline, explore the interactive process flow step:
This step specifically captures the critical operational transition where the sacrificial a-Si dummy gate is cleared over the active 3D fin structures . It demonstrates how plasma etch parameters, selectivity controls, and surface passivation rules execute within the active line sequence to establish the pristine open gate cavity required for replacement metal gate integration .
Related Learning Paths
To further deepen your understanding of 7nm logic integration, review these closely related technical articles:
- Explore the foundational architecture and complete module sequence in the 7nm FinFET process flow .
- Examine the downstream metal fill, work-function tuning, and dielectric deposition mechanisms in the 7nm FinFET gate stack integration process flow .
Future Outlook
As logic scaling moves beyond the 7nm node into sub-3nm regimes, the physical limits of dummy gate etch over vertical fins have driven fundamental structural innovations .
7nm FinFET Architecture Sub-3nm Gate-All-Around (GAA) Nanosheet
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| Wrap-Around Dummy Gate | | Interleaved Sacrificial Stack |
| (3-Side Channel Surface Exposure)| | (SiGe Sacrificial Sheets / Si Channel Sheets) |
+-----------------------------------+ +-----------------------------------------------+
| |
v v
+-----------------------------------+ +-----------------------------------------------+
| Vertically Directional Plasma RIE | | 3D Isotropic Chemical Selective Sheet Release |
| High Selectivity to Oxide Skin | | Near-Infinite Selectivity of SiGe vs [P3]. Si |
+-----------------------------------+ +-----------------------------------------------+
1 (Engineering Practice). Gate-All-Around (GAA) Nanosheet Integration: In GAA nanosheet architectures, simple directional plasma etching of an a-Si dummy gate is no longer sufficient , . Dummy gate removal expands into a complex, two-part sacrificial matrix clearance: removing the external dummy gate stack followed by the highly selective isotropic lateral etching of alternating silicon-germanium (SiGe) sacrificial nanosheet layers relative to single-crystal silicon channels , . 2. Atomic Layer Etching (ALE): To completely eliminate physical sputtering damage and achieve true self-limiting atomic precision, dry etching is transitioning toward thermal and plasma-assisted atomic layer etching (ALE) . ALE utilizes sequential, self-limiting surface modification reactions (such as localized fluorination or chlorination) followed by chemical complexation and desorption, removing exactly one atomic monolayer per cycle without damaging underlying fin surfaces (Engineering Practice). 3. Cryogenic Etching Chemistry: Lowering wafer stage temperatures down to cryogenic regimes alters surface adsorption dynamics, suppressing isotropic radical attack on sidewalls while enabling highly directional radical-assisted etching at ultralow ion energies . This provides an expanded process window for extreme selectivity over ultra-thin oxide skins (Engineering Practice).