A void is a region where the intended material is absent. Its significance depends on where it lies and what that material was supposed to do. A void in dielectric isolation and a void in a metal connection may look similar in a drawing while affecting very different physical functions.
Separate formation from consequence
A cavity can remain unfilled if growth near its entrance restricts access before the interior fills. Other discontinuities can develop during subsequent material transformation or redistribution. A seam, an open pore and a closed cavity are not automatically identical structures.
The final appearance therefore does not uniquely identify the formation mechanism. Equally, naming the deposition method does not establish that every observed void came from that initial step. Some metal voids arise later through transport and stress-related evolution rather than being left directly by deposition.
Process map
A selected 2-step learning trail in 14nm FinFET
Examine why isolation trenches receive oxide fill before their final surface is planarized.
Real step names, layer-by-layer cross-sections, and rationale live inside the 14nm FinFET course, unlocked by account access.
The same empty region interrupts different jobs
| Location | Intended material function | Questions raised by a void |
|---|---|---|
| Isolation dielectric | Separate regions and support an intended interface/geometry | Does the defect alter local fields, continuity or access for later processing? |
| Contact or via metal | Carry current through a connection | Does it narrow or interrupt the conducting path? |
| Metal line | Carry current along a level | Where does current crowd around the missing material? |
| Temporary fill | Support a later process operation | Is the later patterning or removal handoff affected? |
The table identifies questions, not guaranteed failures. A void's connection to a surface and its location relative to a critical path can matter as much as its visual size.
Why dielectric absence does not automatically create a short
An empty cavity is not itself a metal bridge. To claim a short, one must identify a conducting path. Nevertheless, a dielectric void can change the intended field distribution or become accessible to later materials if it connects to the surface. Its consequences depend on the surrounding structure and later sequence.
For metal, an enclosed void can reduce the effective current-carrying section without producing a completely open circuit. A discontinuity across the entire conducting path is a different condition. Conflating these cases makes every void sound like the same electrical failure.
A two-pass interpretation exercise
First trace the material function before considering a defect: isolation, conduction or temporary support. Then insert the void into that path and ask what has changed. If you cannot identify the affected function, you are probably inferring too much from the picture.
Next ask whether a later operation changes the void's accessibility. A buried cavity that becomes exposed during planarization can create a different handoff from one that remains sealed. This does not establish a universal failure, but it explains why the sequence after filling belongs in the analysis.
Conformal coating is not synonymous with complete filling. Conversely, engineered metal growth can fill some cavities more effectively than a purely conformal picture suggests. Published copper electrodeposition research demonstrates that distinction, without making it universal across materials or structures.
Source links
References
Silicon VLSI Technology - Full
James D. Plummer, Michael D. Deal, Peter B. Griffin
Silicon VLSI Technology · ISBN 978-0130850379
Damascene copper electroplating for chip interconnections
P. C. Andricacos, C. Uzoh, J. Dukovic, J. Horkans, H. Deligianni · IBM Journal of Research and Development