7nm Fin Recess Mechanism: Physics, Integration, and Fin Height Control

Function in the Complete Flow

In sub-10nm logic manufacturing, the fin recess etch serves as the critical dimensional-setting step that transforms a planarized shallow trench isolation (STI) dielectric landscape into exposed three-dimensional conducting channel fins. Shallow trench isolation achieves electrical isolation of active areas by forming trenches in the silicon substrate around active elements and backfilling them with insulating dielectrics such as silicon dioxide . Following deep silicon trench etching and subsequent STI gap-fill, the active silicon fins remain buried beneath bulk dielectric oxide.

The primary function of the fin recess module is to selectively step back the trench oxide relative to the single-crystal silicon fin sidewalls without degrading the active channel geometry or crystal quality. This controlled exposure establishes the effective conducting channel height ($H_{fin}$) of the FinFET architecture. Because the total effective channel width of a tri-gate structure is defined by $W_{eff} = 2 \times H_{fin} + W_{fin}$, any spatial or kinetic non-uniformity during the recess etch directly impacts drive current capability, threshold voltage, and short-channel control. Within a comprehensive 7nm FinFET process flow, this step is deliberately integrated after high-temperature well formation and activation anneals. Performing fin recess after thermal budget-intensive anneals prevents dopant redistribution and stress relaxation that would otherwise occur if exposed 3D fin geometries were subjected to high thermal cycles.

+-------------------------------------------------------------+
| Upstream: Planarized STI Oxide & Well-Annealed Buried Fins  |
+-------------------------------------------------------------+
                              |
                              v
+-------------------------------------------------------------+
| 7nm Fin Recess Etch (Selective Oxide Etch-Back)             |
|  - Timed removal of oxide top layer                         |
|  - Uncovering crystalline active Si fin sidewalls           |
+-------------------------------------------------------------+
                              |
                              v
+-------------------------------------------------------------+
| Downstream: Exposed 3D Channel Fins ($H_{fin}$ Established) |
|  - Ready for PTS Ion Implantation & HKMG RMG Modules        |
+-------------------------------------------------------------+

Upstream Input State and Topological Integration

Prior to executing the fin recess, upstream module sequence establishes key structural and material conditions:

• Topographical Planarization: Chemical mechanical planarization (CMP) provides a polished dielectric surface co-planar with or slightly above the protective hardmask atop the silicon fins. Residual dishing across wide isolation fields introduces baseline height variations prior to etch initiation.
• Trench Surface Preparation: High-temperature liner oxidation is employed at trench sharp edges for corner-rounding to reduce localized stress and undesirable electrical effects [P3].
• Dielectric Densification: The trench oxide fill, often deposited via flowable chemical vapor deposition (FCVD), undergoes post-deposition steam and thermal annealing to transform the porous film into a dense siloxane lattice. Residual nitrogen pockets or density gradients within narrow inter-fin gaps can locally perturb chemical etch rates.
• Thermal Budget Sequencing: Well dopant implants and high-temperature activation anneals are completed prior to recessing the STI oxide. This sequencing ensures the baseline fin geometry remains structurally stable and unexposed during peak thermal processing.

Physical and Chemical Mechanisms

The fin height control mechanism relies on highly selective wet chemical etch-back or specialized dry vapor/atomic layer etching to remove silicon dioxide while preserving crystalline silicon.

  Planarized STI State                 Post-Recess Exposed Fin State
  +---+   +-------+   +---+             +---+               +---+
  |   |   | Oxide |   |   |             |   |               |   |
  | Si|   | Fill  |   | Si|             | Si|   Oxide       | Si|
  |Fin|   |       |   |Fin|     ===>    |Fin|   Recess      |Fin|
  |   |---|-------|---|   |             |   |  +-----+      |   |
  |   |   |       |   |   |             |   |  | STI |      |   |
  +---+---+-------+---+---+             +---+--+-----+------+---+

Chemical Dissolution Kinetics

When liquid-phase buffered hydrofluoric acid (BHF)—containing HF and ammonium fluoride (NH4F) buffering agents—is utilized, oxide removal proceeds through the reaction of bifluoride species (HF2-) with siloxane (Si-O-Si) bonds to yield soluble hexafluorosilicates:

$$\text{HF} + \text{F}^- \rightleftharpoons \text{HF}_2^-$$

$$\text{SiO}_2 + 2\text{HF}_2^- + 2\text{H}^+ \rightarrow \text{SiF}_6^{2-} + 2\text{H}_2\text{O}$$

The local dissolution rate depends on the densification state of the oxide network. Regions with unreacted Si-N bonds or local voiding show altered chemical reaction kinetics, making thorough densification annealing critical for cross-wafer fin height uniformity.

Directionality vs. Selectivity Tradeoffs

Process design balances directional plasma action against chemical selectivity, as more physical etch processes gain directionality at the expense of material selectivity [T1]. While plasma-assisted reactive ion etching (RIE) offers anisotropic profile control, direct ion bombardment on active fin sidewalls can introduce lattice dislocations and surface damage that degrade carrier mobility.

Consequently, wet chemical recess or vapor-phase etching is utilized for its high chemical selectivity of SiO2 over crystalline Si. Rather than relying on automatic stopping, precise timing and concentration controls are required to prevent unintended silicon consumption and preserve surface integrity. Because wet chemical etching is inherently isotropic, oxide drops vertically while simultaneously clearing residual native oxides laterally from fin sidewalls.

Aspect-Ratio Dependent Transport

In narrow inter-fin spaces, reactant diffusion and reaction product removal can become mass-transport limited. Capillarity effects in dense arrays may cause micro-loading, where the oxide recess rate in dense fin regions lags behind that in isolated fields. Managing bath fluid dynamics and surfactant chemistry mitigates these spatial loading discrepancies.

Downstream Impact and Failure Propagation

Because the fin recess etch sets the vertical channel height, process variations propagate directly into electrical performance and yield:

+------------------------------------------------------------------------+
|                      FIN RECESS PROCESS VARIATIONS                      |
+------------------------------------------------------------------------+
                     /                                  \
                    /                                    \
                   v                                      v
     [ Over-Recess / Deep Exposure ]          [ Under-Recess / Shallow Exposure ]
                   |                                      |
     +-------------+-------------+          +-------------+-------------+
     |                           |          |                           |
     v                           v          v                           v
 Higher Sub-Fin           Gate-to-Substrate  Reduced Effective       Degraded Drive
 Leakage & PTS            Capacitance        Channel Width           Current (Ion) &
 Punch-through            Increase           ($W_{eff}$)             SCE Mismatch 

Over-Recess and Sub-Fin Parasitics

If the etch depth exceeds target specifications, the oxide floor drops below the intended punch-through stop (PTS) doping plane, uncovering the heavily doped sub-fin region:

• Parasitic Sub-Fin Conduction: When the replacement metal gate electrode is deposited, it wraps around the lower sub-fin area. Gate modulation of regions with sub-optimal dopant profiles increases off-state leakage current ($I_{off}$).
• Parasitic Capacitance Increase: Deeper metal gate extension into isolation trenches increases gate-to-substrate parasitic capacitance ($C_{g,sub}$), reducing switching speed.
• Mechanical Aspect-Ratio Risk: Excessively tall, thin silicon fins exhibit high structural aspect ratios, increasing susceptibility to fin bending or pattern collapse during rinse drying.

Under-Recess and Drive Current Penalty

Conversely, incomplete oxide removal leaves active channel area buried beneath the STI dielectric:

• Drive Current Reduction: A lower $H_{fin}$ directly reduces $W_{eff}$, causing a proportional decrease in saturation drive current ($I_{on}$).
• Threshold Voltage Shifts: Altered electrostatic coupling shifts the threshold voltage ($V_t$), creating timing skew across adjacent logic cells.
• SRAM Noise Margin Mismatch: Die-level non-uniformities in fin recess depth induce local drive current imbalances, degrading SRAM static noise margins. For detailed context on STI module integration, see the 7nm FinFET shallow trench isolation process flow.

Walk the Real Step

To examine where this operation resides within the broader integration sequence, review the step-by-step flow documentation.

Open STI Step 93 in the interactive flow

This step highlights the physical transition where dielectric wet etch-back clears oxide from active channel sidewalls, defining target fin height across dense and isolated transistor regions.

Related Learning Paths

To deepen your understanding of sub-10nm logic modules, explore these adjacent integration topics:

• Self-Aligned Quadruple Patterning (SAQP): Spacer deposition and etch-back principles used to generate dense fin arrays prior to trench isolation.
• FCVD Oxide Densification: Chemical reaction kinetics of curing and steam anneals that convert organosilicon precursors into high-density SiO2 fills.
• Replacement Metal Gate (RMG) Integration: Work-function metal stack deposition over 3D active fins to set target threshold voltages.

Future Outlook

As device architectures evolve beyond FinFETs toward Gate-All-Around (GAA) nanosheets and complementary FETs (CFETs), traditional STI oxide recess is accompanied by isotropic sacrificial layer release. In GAA flows, selective etching of SiGe sacrificial layers relative to Si nanosheets creates suspended channel channels.

  Traditional FinFET Recess              GAA Nanosheet Selective Release
     +---+        +---+                     +===+ Silicon Nanosheet
     |   |        |   |                     ----- SiGe Released Gap
     | Si|  Oxide | Si|                     +===+ Silicon Nanosheet
     |   | Recess |   |                     ----- SiGe Released Gap
  +--+---+--------+---+--+               +--+-------------------+--+
  |    Substrate STI     |               |    Substrate Isolation   |
  +----------------------+               +--------------------------+

Advanced dry atomic layer etching (ALE) techniques increasingly complement wet chemical processing, offering monolayer-level etch depth control. Paired with optical critical dimension (OCD) scatterometry feedback, these mechanisms preserve fin and nanosheet height uniformity across multi-patterned wafers.