7nm Fin Recess Mechanism: Physics, Integration, and Fin Height Control

Function in the Complete Flow

In sub-10nm logic manufacturing, the 7nm fin recess mechanism serves as the definitive structural boundary step that converts planar-planar trench oxide backfills into exposed three-dimensional channel conducting fins [P1], [P2]. Following deep silicon etching driven by self-aligned quadruple patterning (SAQP) and subsequent shallow trench isolation (STI) gap-fill, the active silicon fins remain buried beneath bulk silicon dioxide [T1], [A1]. The primary function of the fin recess etch 7nm module is to selectively step back the dielectric oxide relative to the single-crystal silicon fin sidewalls without eroding the active channel or changing its crystal integrity [P2], [A2].

This controlled exposure—often referred to as SAQP fin exposure—establishes the effective conducting channel height ($H_{fin}$) of the 7nm Fin-shaped Field-Effect Transistor (FinFET) architecture [P2], [T2]. Because the effective width of a tri-gate channel is mathematically defined by $W_{eff} = 2 \times H_{fin} + W_{fin}$, any spatial or kinetic variation during the fin recess directly alters drive current capability, threshold voltage, and short-channel integrity [T2], [P4]. Within the context of a comprehensive 7nm FinFET process flow, this module receives a planarized STI oxide landscape and hands off pristine, uniform silicon fins ready for punch-through stop implantation, sacrificial oxide growth, and eventual replacement metal gate (RMG) patterning [A1], [P4].

+-------------------------------------------------------------+
| Upstream: Post-CMP STI Oxide & Buried Active Silicon Fins   |
+-------------------------------------------------------------+
                              |
                              v
+-------------------------------------------------------------+
| 7nm Fin Recess Etch (Oxide Etch-back / Wet BHF Chemistry)   |
|  - Controlled removal of dielectric top layer                |
|  - Uncovering crystalline active Si fin sidewalls            |
+-------------------------------------------------------------+
                              |
                              v
+-------------------------------------------------------------+
| Downstream: Exposed 3D Channel Fins ($H_{fin}$ Established)   |
|  - Ready for PTS Ion Implantation & HKMG RMG Modules        |
+-------------------------------------------------------------+

Upstream Input State

Prior to executing the fin recess, upstream processing modules establish structural and chemical boundaries that directly influence etch performance [P2], [A1]:

• Mechanical Planarization Topography: Chemical mechanical planarization (CMP) delivers a polished surface where the tops of the hardmask-capped silicon fins are co-planar with the top surface of the flowable chemical vapor deposition (FCVD) oxide [P2], [A1]. Residual polish dishing across wide isolation oxide fields creates spatial height non-uniformities prior to etch initiation (Engineering Practice).
• Dielectric Material Density Gaps: The trench oxide fill relies on FCVD to achieve void-free gap filling between narrow fin pitches [P2]. However, as-deposited FCVD oxide consists of a metastable silazane or low-density oligomer network containing residual nitrogen species and hydroxyl radicals [P2]. Post-deposition ozone curing, UV exposure, and steam thermal annealing transform this porous film into a dense silicon dioxide lattice [P2]. If aging time or thermal budget is insufficient, local nitrogen-rich pockets or low-density micro-voids remain within the trench core [P2].
• Hardmask and Nitride Capping: Silicon nitride spacers and hardmasks generated during SAQP patterning protect the top of the silicon fin [T1], [P1]. The physical integrity of these caps prevents direct downward silicon consumption during dry or wet recess processing [T1].
• Sub-Surface Lattice Strain: Prior deep trench etching and sidewall oxidation steps impart local mechanical strain profiles along the fin base [P3], [A2]. The surface native oxide on the fin sidewalls exhibits non-uniform stoichiometry, requiring strict pre-cleaning before main recess etching [P2].

Physical and Chemical Mechanisms

The FinFET fin height control mechanism operates via isotropic wet chemical etch-back or highly controlled dry atomic layer etching (ALE) to achieve pristine selective removal of silicon dioxide over crystalline silicon [P2], [A1].

  Planarized STI State                 Post-Recess Exposed Fin State
  +---+   +-------+   +---+             +---+               +---+
  |   |   | Oxide |   |   |             |   |               |   |
  | Si|   | Fill  |   | Si|             | Si|   Oxide       | Si|
  |Fin|   |       |   |Fin|     ===>    |Fin|   Recess      |Fin|
  |   |---|-------|---|   |             |   |  +-----+      |   |
  |   |   |       |   |   |             |   |  | STI |      |   |
  +---+---+-------+---+---+             +---+--+-----+------+---+

Chemical Reaction Kinetics in Oxide Etch-Back

When using liquid-phase buffered hydrofluoric acid (BHF)—composed of hydrofluoric acid (HF) and ammonium fluoride ($\text{NH}_4\text{F}$) acting as a pH buffer—the primary chemical dissolution of silicon dioxide follows a multi-step thermodynamic equilibrium [P2]:

$$\text{HF} + \text{F}^- \rightleftharpoons \text{HF}_2^-$$

$$\text{SiO}_2 + 2\text{HF}_2^- + 2\text{H}^+ \rightarrow \text{SiF}_6^{2-} + 2\text{H}_2\text{O}$$

The bifluoride species ($\text{HF}_2^-$) attacks the siloxane ($\text{Si-O-Si}$) bonds in the dielectric network (Engineering Practice). The liquid reaction rate is extremely sensitive to the local condensation state and structural density of the silica network [P2]. In regions where FCVD oxide has not been fully converted into dense $\text{SiO}_2$, residual silicon-nitrogen ($\text{Si-N}$) bonding alters the chemical reaction order, causing localized etch rate deceleration or accelerated pit formation [P2]. Achieving strict 7nm shallow trench isolation baseline stability requires thermal treatments that drive out residual nitrogen completely, homogenizing the dissolution kinetics throughout the trench [P2].

Isotropic vs. Anisotropic Etch Selectivity

While plasma-based reactive ion etching (RIE) offers high directionality, pure dry etching of STI oxide often suffers from pattern loading effects, severe micro-loading between dense and isolated fin arrays, and lattice damage on the exposed silicon sidewalls [P2], [P3]. Dry plasma processes introduce high-energy ion bombardment that leaves residual lattice dislocations along the channel surfaces, degrading electron and hole mobility [P3], [A2].

Consequently, wet chemical recess (or vapor-phase HF etching) is favored for its near-infinite etch selectivity of $\text{SiO}_2$ over crystalline Si [P2]. Because liquid etching is inherently isotropic, the oxide recesses vertically while simultaneously clearing oxide laterally from the fin sidewalls [P1], [P2]. The chemical selectivity ensures that once the native oxide is removed, the single-crystal silicon fin remains undamaged with atomic-scale smoothness [P2], [A1].

Physics of Fin Corner Rounding and Profile Taper

As the STI oxide level drops beneath the active target line, the transition region between the exposed fin sidewall and the buried STI oxide floor experiences stress concentration [P3], [A1]. The local etch rate can be influenced by capillary action in tight inter-fin spaces and localized chemical transport limitations (Engineering Practice). If the sidewall oxide profile develops an unwanted taper or scalloping, subsequent metal gate filling becomes prone to voiding, leading to degraded subthreshold swing ($SS$) and increased drain-induced barrier lowering ($DIBL$) [P3], [P4].

Downstream Impact and Failure Propagation

Because the fin recess etch 7nm step determines the final vertical channel dimensions, process deviations at this stage propagate directly into transistor electrical behavior and structural yield [P2], [P4]:

+------------------------------------------------------------------------+
|                      FIN RECESS PROCESS VARIATIONS                      |
+------------------------------------------------------------------------+
                     /                                  \
                    /                                    \
                   v                                      v
     [ Over-Recess / Deep Exposure ]          [ Under-Recess / Shallow Exposure ]
                   |                                      |
     +-------------+-------------+          +-------------+-------------+
     |                           |          |                           |
     v                           v          v                           v
 Higher Sub-Fin           Gate-to-Substrate  Reduced Effective       Degraded Drive
 Leakage & PTS            Capacitance        Channel Width           Current (Ion) &
 Punch-through [P2,T2]   Increase [P4]      ($W_{eff}$) [T2]        SCE Mismatch [P4]

Over-Recess and Sub-Fin Leakage

If the etch depth exceeds the designed baseline, the oxide floor drops below the intended punch-through stop (PTS) dopant profile [T2], [A1]. This deep exposure uncovers the lower, more heavily doped bulk silicon region [T2]. When the high-$k$ metal gate (HKMG) structure is subsequently deposited during the replacement gate module, the gate electrode wraps around this lower sub-fin area [P3].

• Sub-Fin Parasitic Conduction: The gate electrode modulates regions with sub-optimal dopant profiles, increasing off-state leakage current ($I_{off}$) via parasitic sub-surface channels [T2].
• Increased Parasitic Capacitance: Deeper metal gate extensions into the trench increase gate-to-substrate capacitance ($C_{g,sub}$), slowing down circuit switching speed and raising dynamic power consumption [P4], [T2].
• Mechanical Instability: Uncovering overly tall, thin silicon fins increases their aspect ratio, making them susceptible to physical bending or pattern collapse during subsequent rinse drying steps [P3].

Under-Recess and Drive Current Loss

Conversely, insufficient oxide removal leaves active channel height buried under the dielectric [P2].

• Drive Current Reduction: A reduction in $H_{fin}$ directly reduces the effective channel width $W_{eff}$, leading to a proportional loss in saturation drive current ($I_{on}$) [T2], [P4].
• Threshold Voltage Shift: The altered electrostatic coupling shifts the threshold voltage ($V_t$), causing circuit-level timing mismatches between adjacent logic cells [P4], [T2].
• Asymmetric Channel Profile: Non-uniform recess across a die creates local variations in $V_t$ and $I_{on}$, severely degrading static random-access memory (SRAM) noise margins (Engineering Practice).

Material Non-Uniformities and Defect Traps

Metastable FCVD oxides with unreacted nitrogen or localized density variations lead to uneven recess surfaces, commonly called "oxide micro-trenching" or "rough oxide floors" [P2]. These local structural defects act as electric field concentration points, increasing gate dielectric breakdown risks during high-voltage stress operations [P3], [P4]. For a broader perspective on dielectric integration, explore the 7nm FinFET shallow trench isolation process flow [A2].

Walk the Real Step

To examine where the fin recess operation resides within the complete lithographic and etch integration sequence, inspect the step-by-step interactive flow documentation (Engineering Practice).

Open STI Step 93 in the interactive flow

This step highlights the exact physical transition where STI oxide wet etch-back clears the dielectric from the active silicon channel top, exposing the three-dimensional fin sidewalls while controlling the baseline target height across dense and isolated transistor regions [P2], [A1].

Related Learning Paths

To deepen your understanding of sub-10nm transistor modules, consider these adjacent process architecture topics:

• Self-Aligned Quadruple Patterning (SAQP): Master the spacer deposition and etch-back principles used to generate hyper-dense silicon fin arrays prior to isolation trench formation [P1], [P4].
• Flowable Chemical Vapor Deposition (FCVD) Densification: Study the chemical reaction kinetics of ambient aging, curing, and steam annealing that convert organosilicon precursors into dense, defect-free $\text{SiO}_2$ fills [P2].
• Replacement Metal Gate (RMG) Integration: Learn how multi-work-function metal stacks encapsulate the exposed 3D active fins to establish target threshold voltages without inducing gate fill voids [P3], [P4].

Future Outlook

As device architectures transition beyond 7nm FinFETs toward gate-all-around (GAA) nanosheets and complementary FETs (CFETs), the classical oxide recess mechanism undergoes profound evolution [P1], [A1]. In GAA architectures, the traditional STI recess step is augmented by highly selective isotropic sacrificial layer removal, where silicon-germanium ($\text{SiGe}$) sacrificial sheets are etched away relative to silicon nanosheets [A1].

  Traditional FinFET Recess              GAA Nanosheet Selective Release
     +---+        +---+                     +===+ Silicon Nanosheet
     |   |        |   |                     ----- SiGe Released Gap
     | Si|  Oxide | Si|                     +===+ Silicon Nanosheet
     |   | Recess |   |                     ----- SiGe Released Gap
  +--+---+--------+---+--+               +--+-------------------+--+
  |    Substrate STI     |               |    Substrate Isolation   |
  +----------------------+               +--------------------------+

Furthermore, atomic layer etching (ALE) is replacing conventional wet chemical etching to enable monolayer-level control over dielectric recess depths [P1]. Combined with advanced optical critical dimension (OCD) scatterometry and X-ray metrology, real-time feedback loops ensure atomic-scale fin height uniformity across multi-patterned wafers, preserving electrostatic integrity for future technology generations [P1], [P4].