28nm STI CMP Mechanism: Planarization Physics, Interfacial Chemistry, and Defect Control

Function in the Complete Flow

In advanced integrated circuit manufacturing, shallow trench isolation (STI) serves as the primary structural boundary preventing parasitic leakage currents and latch-up between adjacent transistors [P1, T1]. Within the 28nm Planar process flow, the chemical mechanical planarization (CMP) module acts as the critical bridge between sub-surface trench patterning and planar gate formation [P2, T1].

Prior to shallow trench isolation CMP, active regions are defined by etching deep micro-scale trenches into the silicon substrate and refilling the resulting topography with an insulating dielectric overburden [P2, T1]. The primary function of STI chemical mechanical polishing is to selectively remove this excess oxide overburden while terminating abruptly on a underlying silicon nitride stop layer [P1, P3]. By terminating cleanly on the hard mask, STI oxide planarization 28nm planar CMOS integration achieves a globally flat surface topology where dielectric material remains strictly confined inside the isolation trenches [P1, P3].

This planarization step hands off a coplanar surface structure to downstream wet chemical etch modules that strip the remaining protective nitride mask [P1, T1]. Without high-precision STI CMP, topography height variations across dense and sparse active patterns would corrupt subsequent photolithographic depth-of-focus margins, resulting in critical dimension distortion during high-k metal gate definition [P3, T1].

Incoming Structure: Topographical Oxide Overburden over Nitride-Masked Trenches
                                   │
                                   ▼
             ┌──────────────────────────────────────────┐
             │       28nm STI CMP Step Processing       │
             │   (Chemically Assisted Surface Abrasion) │
             └──────────────────────────────────────────┘
                                   │
                                   ▼
Outgoing Structure: Coplanar Trench Dielectric & Active Hard Mask Interface

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Upstream Input State

The structural and chemical incoming state inherited by the STI CMP process is determined by prior etch and chemical vapor deposition (CVD) steps [P2, T1]. The wafer surface entering this step exhibits severe topography variations and complex film stress distributions that directly dictate polishing dynamics [P3, T1].

The upstream stack on the active areas consists of: 1 (Engineering Practice). Bulk Silicon Substrate: Etched with straight or slightly tapered trench sidewalls to prevent void formation during dielectric fill [P2, T1]. 2. Pad Oxide Layer: A thermally grown silicon dioxide layer that relieves interfacial strain between the silicon substrate and the overlying nitride film [P1, T1]. 3. Nitride Stop Layer: A stoichiometric silicon nitride film deposited via low-pressure chemical vapor deposition that acts as a hard mask during trench etching and a mechanical stop layer during CMP [P1, T1]. 4. Trench Isolation Dielectric Overburden: A thick silicon dioxide film deposited by high-density plasma chemical vapor deposition (HDP-CVD) or high-aspect-ratio deposition techniques [T1].

Because non-selective oxide deposition covers both isolated trenches and elevated active area patterns, the wafer presents significant step-height differences [P1]. Elevated regions over dense active patterns experience high local contact pressures during polishing, whereas wide recessed trench field oxide areas experience delayed mechanical contact [P3]. Additionally, local pattern density variations across logic core areas, memory blocks, and dummy feature regions generate within-die (WID) loading effects [P3]. The STI CMP process must overcome these structural variations without causing severe erosion of the thin silicon nitride stop layer [P1, P3].

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Physical and Chemical Mechanisms

The fundamental physics of 28nm shallow trench isolation CMP relies on the synergistic coupling of surface chemical reactions and mechanical contact wear, broadly classified as a "chemical softening + mechanical removal" mechanism [P1]. In high selective slurry (HSS) CMP formulations, planarization efficiency is driven primarily by molecular affinity rather than pure mechanical grinding [P1, P3].

                     [ Ceria Abrasive Particle (CeO2) ]
                                     │
                             Ce-O-Si Reaction
                                     │
                                     ▼
[ Softened Hydrated Oxide Layer ] ──> Shear Force Removal ──> [ Solubilized Silicates ]
                                     ▲
                                     │
                  [ Polymeric Inhibitor Passivation Layer ]
                                     │
                        [ Silicon Nitride Surface (Si3N4) ]

1 [P1]. Oxide Softening and Chemical Binding Mechanics

Traditional dielectric CMP relies on silica abrasives in alkaline media, but STI CMP predominantly utilizes cerium oxide (ceria) slurry particles [P1]. Ceria particles feature surface oxygen vacancies and variable valence states that exhibit strong chemical reactivity toward silicon dioxide [P1]. When ceria abrasives contact the hydrated silicon oxide surface under mechanical shear, temporary chemical bonds form across the solid-liquid interface [P1, P3]:

$$\text{Ce-OH} + \text{HO-Si} \rightleftharpoons \text{Ce-O-Si} + \text{H}_2\text{O}$$

This reversible surface chemical reaction dramatically lowers the mechanical energy barrier needed to sever siloxane backbones [P1]. As the polishing platen rotates, hydrodynamic shear forces break these softened surface silicate complexes, transferring microscopic dielectric fragments away from the substrate [P1].

2. Nitride Stop Layer Passivation Mechanism

Achieving extreme removal selectivity between silicon dioxide and the silicon nitride stop layer CMP mechanism is vital [P1]. To prevent polish-through into the underlying active silicon, nitrogen-containing or carboxylate-terminated polymeric additives are incorporated into the slurry [P1].

The chemical state of the polish environment is tailored through controlled pH adjustments [P1]. At the operating pH, the surface zeta potential of silicon nitride differs markedly from that of silicon dioxide [P1]. The cationic or amphiphilic polymeric additives selectively adsorb onto the silicon nitride surface, constructing a protective chemical passivation barrier [P1]. This adsorbed layer induces mechanical suppression, shielding the underlying nitride from physical contact with ceria particles while suppressing hydrolysis of the nitride lattice [P1]. Conversely, the oxide surface remains largely unpassivated, permitting rapid chemical bonding and removal by ceria abrasives, which yields high oxide-to-nitride removal selectivity [P1, P3].

3. Contact Mechanics and Pressure Distribution

From a mechanical perspective, material removal rate ($RR$) across the wafer surface follows the classic Preston relationship, modified for local pattern geometry:

$$RR = K_p \cdot P \cdot V$$

where $K_p$ represents the chemical-mechanical Preston coefficient, $P$ is the localized contact pressure, and $V$ is the relative sliding velocity between the wafer and polishing pad [P3].

On a non-planar wafer surface, protruding oxide step features absorb the bulk of the downforce applied by the polishing head, causing local contact pressure to increase dramatically above the nominal pressure [P3]. Recessed field oxide regions experience minimal localized pressure [P3]. This pressure differential accelerates overburden removal on high spots while preserving recessed oxide, thereby achieving rapid local planarization [P3]. Once global planarity is established, the polishing front reaches the rigid silicon nitride stop layer, at which point the chemical passivation mechanism suppresses further vertical polishing [P1, P3].

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Downstream Impact and Failure Propagation

Because STI CMP establishes the baseline topography for the entire front-end-of-line module, directional shifts in polish parameters directly propagate into severe downstream failure modes [P1, P3].

Process Deviation                    Physical Consequence                   Downstream Failure Mode
─────────────────                    ────────────────────                   ───────────────────────
Excessive Overpolish ──────────────> Field Oxide Dishing ─────────────────> Parasitic Sidewalk Leakage /
                                                                           Subthreshold Degradation

Low Oxide/Nitride Selectivity ─────> Nitride Stop Layer Erosion ─────────> Active Substrate Damage /
                                                                           Scratch Defectivity

Under-polishing / Residual Oxide ──> Blocked Nitride Strip ──────────────> Active Area Bridging Shorts /
                                                                           Patterning Failure

1 [P3]. Trench Oxide Dishing and Active Sidewall Exposure

If the mechanical polishing duration is extended beyond the optimal endpoint or if pad elasticity is overly soft, localized overpolishing occurs in wide isolation trenches [P1, P3]. This phenomenon, known as oxide dishing, causes the center of the field oxide to recede below the level of the active silicon interface [P1, P3].

During subsequent gate oxide formation and polysilicon/metal gate deposition, gate material wraps around the exposed upper corners of the active silicon trench [P2]. This non-planar gate topography induces electric field concentration at the active area corners, lowering the local threshold voltage [T3]. As a result, the device suffers from parasitic corner conduction, increased subthreshold swing, and elevated off-state leakage current ($I_{\text{off}}$) [T3].

2. Nitride Hard Mask Erosion and Active Substrate Damage

When chemical selectivity degrades or local downforce fluctuates, the ceria abrasives mechanically erode the thin silicon nitride stop layer [P1, P3]. Non-uniform nitride removal degrades within-die hard mask thickness uniformity [P3]. In severe cases, complete local removal of the nitride mask exposes the underlying monocrystalline silicon active area to abrasive plowing, introducing micro-scratches, subsurface lattice dislocations, and metallic contamination [P1]. These mechanical defects serve as non-radiative recombination centers and thermal leakage paths, severely degrading gate oxide integrity and carrier mobility [T1, T3].

3. Oxide Overburden Residue

Conversely, under-polishing leaves residual silicon dioxide patches on top of the silicon nitride stop layer [P1]. Because hot phosphoric acid wet etch chemistry selectively removes silicon nitride while exhibiting near-zero etch rates on silicon dioxide, residual oxide acts as a micro-masking barrier [P1, T1]. During post-CMP nitride removal, the masked nitride regions remain unetched, leading to topological active area defects that cause lithographic bridging shorts during gate patterning [P2, T1].

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Walk the Real Step

To understand how these physical and chemical principles are implemented in integrated manufacturing, examine the operational step details within the sequence module [P2].

You can inspect the exact integration context by opening the interactive flow tool:

• Open STI Step 21 in the interactive flow

In this process step, the incoming wafer featuring HDP oxide overburden is mounted on a multi-zone carrier head [T1]. The head applies controlled pneumatic downforce profiles to compensate for within-wafer (WIW) incoming film thickness non-uniformities [P3]. The wafer is pressed face-down against a polyurethane polishing pad mounted on a rotating platen, while ceria-based high-selectivity slurry is continuously dispensed [P1, P3]. Optical reflection sensors or motor torque monitoring systems track real-time film removal, identifying the precise transition point where oxide overburden clears and the silicon nitride stop layer is exposed [P1]. Upon endpoint detection, a timed overpolish phase ensures complete clearing across dense and sparse arrays, followed immediately by an in-situ post-CMP cleaning rinse to remove residual ceria particles and prevent slurry drying stains [P1].

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Related Learning Paths

To further master front-end isolation engineering and integration logic in advanced CMOS technology nodes, explore these closely coupled modules:

• Full Module Integration: Review the overarching architectural roadmap in the 28nm Planar process flow article, tracing how front-end isolation connects to gate-first and gate-last HKMG integration [P3].
• Upstream and Downstream STI Modules: Detailed breakdown of trench etching, thermal liner oxidation, HDP dielectric fill, and wet hard-mask stripping is available in the 28nm Planar shallow trench isolation process flow guide [P3].
• Interactive Flow Exploration: Continuously trace physical wafer transformations across the module chain by launching Open STI Step 21 in the interactive flow [T1].

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