28nm Poly Gate Patterning Process Flow: Principles, Photolithography, and Etch Integration

Function in the Complete Flow

In the 28nm Planar process flow, the gate patterning module acts as the central structural bridge between thin-film stack deposition and front-end junction formation. Specifically, the P1 poly photo integration step transforms a continuous, unpatterned gate layer stack into high-density isolated gate lines across active silicon regions.

This single step receives a flat substrate prepared with shallow trench isolation (STI) regions, active silicon channels, a gate dielectric layer, an unpatterned sacrificial or functional polysilicon film, a hard mask layer, an anti-reflective coating (ARC), and a light-sensitive photoresist film. Through critical photolithographic exposure and subsequent dry etching, the module defines the gate critical dimension (CD) and gate length that govern transistor switching speeds.

Once the poly photo and hard mask pattern transfer mechanisms are complete, the resulting patterned polysilicon gate structures act as self-aligned masks for subsequent pocket/extension ion implantations, halo implants, and spacer sidewall depositions. In replacement metal gate integration, the sacrificial polysilicon gate is selectively removed before depositing the functional work-function metals and gate electrode . In modern gate-last architecture implementations, these patterned polysilicon lines function as sacrificial dummy structures that preserve gate cavity dimensions throughout high-temperature source/drain annealing processes before being selectively removed during replacement metal gate (RMG) processing. The precision achieved during 28nm Planar gate stack integration process flow directly dictates downstream contact formation, strain engineering effectiveness, and global circuit performance.

Upstream Input State

Before the gate patterning module begins, the wafer surface inherits a highly engineered multi-layer film stack deposited across active single-crystal silicon channels and isolation oxide structures. Achieving low line-edge roughness (LER) during polysilicon gate lithography requires pristine upstream film uniformity, low defect density, and controlled intrinsic stress states.

The foundational film in this input stack is the gate dielectric layer, which consists of an ultrathin thermal silicon oxide (SiO2), a silicon oxynitride (SiON) film, or a high-k dielectric material such as hafnium oxide (HfO2) deposited via atomic layer deposition (ALD). Immediately above the gate dielectric sits an amorphous or polycrystalline silicon layer, deposited via low-pressure chemical vapor deposition (LPCVD). In replacement metal gate integration, this polysilicon layer serves as a sacrificial dummy material whose structural grain distribution and surface roughness impact photolithographic light reflection and plasma etch uniformity.

To protect the gate stack and define high-aspect-ratio profiles during plasma etching, a hard mask stack comprising silicon nitride (SiN), silicon oxynitride (SiON), or amorphous carbon is deposited over the polysilicon. Above the hard mask, an inorganic or organic anti-reflective coating (ARC) is applied to suppress internal optical interference and standing waves during exposure. Surface pretreatment with adhesion promoters such as hexamethyldisilazane (HMDS) is applied to enhance interfacial bonding before photoresist coating . Finally, a uniform layer of chemically amplified positive photoresist is spin-coated over the ARC. The incoming substrate must exhibit minimal thermal stress warping and flat local topography across active diffusion regions to prevent depth-of-focus degradation during exposure.

Physical and Chemical Mechanisms

The gate pattern transfer mechanism relies on a sequential combination of chemical photolithography and plasma reactive ion etching (RIE) to translate optical mask patterns into vertical polysilicon gate lines.

Photolithographic Exposure and Chemically Amplified Processing

During P1 lithography, deep ultraviolet (DUV) light passes through a quartz photomask carrying the circuit design. Photons absorbed within the photoresist activate photoacid generator (PAG) molecules, creating localized concentration gradients of acid. During the post-exposure bake (PEB) step, thermal energy drives acid-catalyzed cleavage of protective polymer side-chains, rendering the exposed regions soluble in an alkaline aqueous developer solution. The contrast between exposed and unexposed regions forms a developed photoresist pattern with defined feature widths. The underlying anti-reflective coating (ARC) minimizes standing waves by matching optical refractive indices and absorbing back-scattered light from the reflective polysilicon surface.

Hard Mask Pattern Transfer Etch

Because organic photoresist erodes under aggressive fluorocarbon or halogenated plasmas, the pattern must first be transferred into the inorganic hard mask layer. The wafer enters a low-pressure plasma discharge reactor where halogen radicals and accelerated ions attack the exposed hard mask. Fluorocarbon-based gas mixtures generate reactive species that break silicon-nitrogen and silicon-oxygen bonds, while directional ion acceleration provides the mechanical sputtering energy necessary to achieve vertical sidewalls. Once the hard mask etch completes, remaining photoresist and organic ARC layers are stripped using oxygen plasma ash processes to leave a rigid hard mask template over the polysilicon film.

Polysilicon Dry Etching Kinetics

The underlying polysilicon gate patterning is executed using a multi-step plasma etching process consisting of a main etch, soft-landing etch, and over-etch phase. The primary plasma chemistry relies on chlorine (Cl2) and hydrogen bromide (HBr) gases, combined with small oxygen (O2) additions.

The fundamental surface kinetics follow a Langmuir-Hinshelwood mechanism, where neutral bromine and chlorine radicals adsorb onto the polysilicon surface. Directional positive ions from the plasma sheath bombard the horizontal surfaces, supplying kinetic energy to break Si-Si bonds and accelerate the desorption of volatile silicon tetrahalide products like SiCl4 and SiBr4.

To maintain anisotropic verticality and prevent lateral undercut, dynamic sidewall passivation occurs simultaneously. Oxygen radicals react with etched silicon halogens and chamber species to form an ultrathin, non-volatile silicon oxyhalide (SiOxFyClz) passivation film along the vertical sidewalls of the poly gate. Directional ion bombardment continually removes this passivating oxide from horizontal surfaces while leaving vertical sidewalls protected, yielding straight gate profiles.

Plasma Halogen Radicals (Cl, Br) + Energetic Ions
                  │
                  ▼
  ┌───────────────────────────────┐
  │  Adsorption on Poly Surface   │
  └───────────────┬───────────────┘
                  │
                  ▼
  ┌───────────────────────────────┐
  │ Physical-Chemical Reaction    │
  │ (Bond breaking & SiX4 desorp) │
  └───────────────┬───────────────┘
                  │
                  ▼
  ┌───────────────────────────────┐
  │ Dynamic Sidewall Passivation  │
  │  (SiOxFyClz film growth)      │
  └───────────────┬───────────────┘
                  │
                  ▼
  ┌───────────────────────────────┐
  │ High-Selectivity Over-Etch    │
  │   Stops on Gate Dielectric    │
  └───────────────┬───────────────┘

Dielectric Selectivity and Over-Etch Mechanics

As the main etch approaches the underlying gate dielectric, the process transitions to a high-selectivity soft-landing and over-etch chemistry. High etch selectivity is a primary requirement to etch through the polysilicon layer while suppressing erosion of the underlying gate dielectric [T1].

By eliminating fluorine species, increasing HBr ratio, reducing ion acceleration energy, and deploying carbon-coated reactor wall strategies, radical densities are modulated to maximize ion-assisted chemical anisotropy while suppressing dielectric removal rates. The high selectivity ensures complete removal of polysilicon residues in high-density gate regions without degrading the thin gate oxide dielectric underneath.

Downstream Impact and Failure Propagation

Process variations and structural non-idealities introduced during 28nm gate stack integration propagate directly into downstream manufacturing modules and degrade ultimate metal-oxide-semiconductor field-effect transistor (MOSFET) device behavior.

Electrical Performance and Short-Channel Control

Variations in gate critical dimension (CD) directly alter transistor channel length. If the gate length is etched narrower than target specifications, short-channel effects (SCE) intensify, leading to drain-induced barrier lowering (DIBL), threshold voltage roll-off, and increased off-state subthreshold leakage current. Conversely, overly wide poly gate lines reduce drive current and degrade circuit operating frequency. Line-edge roughness (LER) and line-width roughness (LWR) cause localized fluctuations in threshold voltage across the channel width, widening device-to-device electrical variability.

Profile Taper and Gate Footing Failures

Imbalances between sidewall passivation growth and directional ion bombardment cause profile distortions such as footing or tapering. A tapered gate profile creates an asymmetric effective channel length and complicates halo and source/drain extension ion implant profiles. Excessive footing leaves residual polysilicon micro-bridges or stringers between adjacent gate lines, resulting in gate-to-gate short circuits. Conversely, lateral undercut near the gate base degrades gate dielectric integrity and causes severe electric field concentration, triggering premature time-dependent dielectric breakdown (TDDB).

Strain Engineering Amplification in Gate-Last Integration

In a gate-last replacement metal gate process, the structural quality of the sacrificial polysilicon line governs downstream strain mechanics. After source/drain regions are filled with stress-inducing embedded silicon-germanium (SiGe) for p-channel MOS (PMOS) transistors, the dummy polysilicon gate is selectively etched away. The mechanical relaxation occurring upon dummy gate removal amplifies compressive channel strain, significantly boosting hole mobility. If the initial poly gate line exhibits footing or non-uniform top morphology, planarization via chemical mechanical planarization (CMP) will fail to open the dummy gate uniformly, leading to incomplete dummy poly removal and metal fill voids.

Failure Mechanism	Primary Process Root Cause	Direct Impact on 28nm Transistors
Severe Off-State Leakage	Gate CD under-etching / over-exposure	Threshold voltage roll-off and excessive static power dissipation
Gate-to-Gate Shorts	Poly footing / incomplete over-etch	Conductive stringers bridging adjacent gate lines
Early Breakdown (TDDB)	Notch/undercut at dielectric interface	Localized electric field enhancement and gate oxide degradation
Incomplete Metal Gate Fill	Poly profile tapering / CMP non-uniformity	Dummy gate opening failures during replacement metal gate module

Walk the Real Step

To visualize how gate patterning integrates into the broader 28nm manufacturing sequence, explore the exact module step details in the digital flow environment:

Open GATE Step 54 in the interactive flow

This step represents the decisive physical transition where photolithographic mask patterns are permanently carved into the gate stack hard mask and polysilicon layers. Located after the gate film stack deposition and prior to spacer formation and junction doping, Step 54 establishes the precise channel geometry, gate endcap extensions, and isolation land patterns required for high-yield complementary metal-oxide-semiconductor (CMOS) integration.

Related Learning Paths

To deepen your understanding of adjacent modules within the 28nm manufacturing sequence, explore these technical guides:

• Learn about upstream film stack preparation, high-k dielectric deposition, and work function tuning in the planar gate stack integration process flow.
• Understand the complete module sequence, active area definition, and interconnect integration in the comprehensive 28nm Planar process flow.

Future Outlook

As semiconductor technology scales beyond the 28nm planar node into three-dimensional FinFET and gate-all-around (GAA) nanosheet architectures, gate patterning faces unprecedented geometric constraints. Single-exposure lithography gives way to multi-patterning techniques, while traditional reactive ion etching transitions toward atomic layer etching (ALE).

In sub-28nm generations, self-aligned gate endcap (SAGE) structures and surface-passivated plasma reactors are deployed to mitigate line-end pull-back and maintain profile fidelity. Furthermore, advanced chamber wall passivations continue to evolve, enabling precise control over halogen radical fluxes and protecting ultrathin dielectric interfaces during gate pattern transfer.