28nm Planar Gate Stack Integration Process Flow: Principles, Mechanisms, and Integration Logic

Role in the Complete Flow

The 28nm planar gate stack integration is one of the most critical modules in the entire 28nm Planar process flow, sitting at the intersection of channel engineering and source/drain formation [P1]. Upstream, this module receives a wafer that has already completed well formation, channel implantation, and threshold-voltage adjustment implants [A1]. The silicon surface is typically protected by a sacrificial or pad oxide layer that served as a screen during earlier ion implantation steps and as a protective barrier during cleaning operations [T1]. The gate stack module must transform this prepared surface into a device-quality gate dielectric and gate electrode stack that will define the transistor's threshold voltage, drive current, leakage, and long-term reliability [T3].

Downstream, the gate stack delivers the patterned gate electrode that acts as a self-aligned mask for lightly doped drain (LDD) implants, sidewall spacer formation, and source/drain implantation [A1]. Any defect, thickness non-uniformity, or interface contamination introduced in this module propagates directly into the final device's electrical characteristics [T1]. The gate oxide capacitance, for instance, directly controls the threshold voltage through the relationship V_t = V_{FB} + \phi_s + \frac{Q_d}{C_{ox}}, where C_{ox} is inversely proportional to the gate dielectric thickness [T1]. A thinner gate oxide raises C_{ox}, improving drive current and suppressing short-channel effects, but also increases gate tunneling leakage exponentially [T3]. This fundamental tradeoff between performance and leakage is the central tension that the 28nm gate stack integration must navigate [T3].

At the 28nm node, the industry transitioned from conventional silicon oxynitride (SiON) gate dielectrics to high-k metal gate (HKMG) stacks in many process variants, though poly-SiON gate stacks remained in use for certain low-power and planar FD-SOI variants [P2][P3]. The choice between gate-first and replacement gate (gate-last) integration schemes profoundly affects how the gate stack module interacts with thermal budgets and subsequent process steps [P2].

Entry State and Sequence Logic

What the Module Receives

When the GATE module process flow begins, the wafer carries a completed isolation structure — typically shallow trench isolation (STI) — and a defined channel doping profile established through well and channel implants [T1]. The active silicon surface is covered by a pad oxide (sometimes called a screen oxide or sacrificial oxide) that was grown or deposited earlier in the flow to protect the silicon during implantation and cleaning [T1]. This pad oxide is not suitable as a gate oxide: it has been exposed to implant damage, potential contamination, and its thickness was optimized for implant screening rather than for gate dielectric quality [P3].

The 28nm Planar well and channel implant integration process flow has already established the retrograde well profiles and threshold-adjustment implants that determine the channel doping [P1]. The surface silicon quality beneath the pad oxide is critical: any crystal damage, metallic contamination, or particulate residue from upstream steps will be incorporated into the gate dielectric and degrade its reliability [T3].

Sequence Dependencies

The gate stack must be formed after all channel implants are complete but before LDD and source/drain implants [A1]. This ordering is dictated by two competing constraints:

1 (Engineering Practice). Thermal budget: Gate oxide growth and subsequent thermal anneals must occur after channel implants so that the doping profile is activated, but the gate dielectric must be formed before the high-temperature source/drain activation anneals, because excessive post-gate-oxide thermal exposure degrades the Si–SiO₂ interface quality [T3].

2. Self-alignment: The gate electrode serves as the self-aligned mask for LDD and source/drain implants [P3]. If the gate were patterned before channel implant completion, the implant profile would be non-uniform under the gate edge [A1].

In 28nm HKMG gate-first integration, the sequence becomes even more constrained because the high-k dielectric and metal gate materials must survive the subsequent source/drain activation thermal budget [P2]. This is why the gate-first approach requires careful selection of metal gate materials with sufficient thermal stability [P2]. In contrast, the replacement gate approach uses a dummy poly-Si gate during front-end processing and replaces it with the metal gate after all high-temperature steps are complete, decoupling the gate material from thermal budget concerns but adding process complexity [P2].

Physical and Chemical Mechanisms

Pad Oxide Remove for Thick Gate Integration Principles

One of the foundational steps in the gate stack module is the pad oxide remove [T3]. This step is essential because the existing oxide on the silicon surface is too thick and too damaged to serve as the device gate oxide [T3]. As described in fundamental VLSI processing texts, "the thin oxide, which is present over the active areas of each transistor, is first stripped in a dilute hydrofluoric acid (DHF) solution [T1]. HF is a highly selective etchant and will stop etching when the underlying silicon is reached" [T1].

The Pad Oxide Remove for Thick Gate integration principles center on the fact that any oxide grown or deposited for purposes other than gate dielectric use — whether for implant screening, surface protection, or STI-related processing — contains defects, implanted species, and contamination that would compromise gate dielectric integrity if left in place [T3]. The pad oxide remove step ensures that the gate oxide is grown on a pristine silicon surface, yielding a well-controlled interface with predictable electrical characteristics [T1].

The chemical mechanism of the DHF etch is based on the reaction of hydrofluoric acid with silicon dioxide:

SiO_2 + 6HF \rightarrow H_2SiF_6 + 2H_2O

This reaction is highly selective: DHF etches silicon dioxide at a significantly higher rate than it etches silicon, allowing the process to stop reliably at the silicon surface [T1]. However, because the etch is unmasked, it also etches the field oxide (STI) simultaneously (Engineering Practice). The etch must therefore be timed so that excessive field oxide loss is avoided, although minor recessing of the STI surface is generally tolerable [T1].

Gate Oxide Growth

Once the bare silicon surface is exposed, the gate oxide is grown through thermal oxidation [T1]. The growth mechanism follows the Deal-Grove model, where the oxidation rate transitions from a linear (surface-reaction-limited) regime in the initial phase to a parabolic (diffusion-limited) regime as the oxide thickens (Engineering Practice). At 28nm, the gate oxide is extremely thin, placing it firmly in the linear regime where the oxidation rate is controlled by the surface reaction rate at the Si–SiO₂ interface [P3].

The quality of the Si–SiO₂ interface is paramount [T1]. The interface is characterized by a transition region where silicon atoms are sub-oxide bonded, creating interface states that can trap charge and shift the threshold voltage [T2]. A well-grown gate oxide minimizes these interface states through controlled oxidation conditions and post-oxidation annealing [T1][T3].

For 28nm HKMG stacks, the gate dielectric is typically a bilayer: an interfacial silicon oxide layer (grown or deposited) topped by a high-k dielectric such as hafnium oxide (HfO₂) [P2]. The high-k material provides a higher physical thickness for the same equivalent oxide thickness (EOT), reducing the electric field across the dielectric and suppressing tunneling leakage [T2]. The EOT relationship is given by:

EOT = t_{high-k} \times \frac{K_{SiO_2}}{K_{high-k}}

where t_{high-k} is the physical thickness of the high-k layer, and K values are the respective dielectric constants [T2]. Because K_{high-k} is significantly larger than K_{SiO_2}, a thicker physical layer achieves the same EOT, reducing defect generation and tunneling probability [P2].

Gate Electrode Formation

For poly-SiON gate stacks, the gate electrode is deposited polysilicon, which offers compatibility with silicon processing and the ability to withstand high-temperature anneals required after self-aligned source/drain implantation [T2]. The polysilicon work function can be tuned by doping it n-type or p-type, providing the flexibility needed for symmetric CMOS technology [T2].

A key limitation of poly-Si gates is the polysilicon depletion effect: under inversion conditions, a depletion region forms at the polysilicon–gate oxide interface, effectively increasing the gate dielectric thickness and reducing C_{ox} [T3]. This effect becomes severe as the gate oxide is scaled thin, and it was one of the primary motivations for transitioning to metal gates at the 28nm node [T2][P2]. Metal gates eliminate the depletion effect and provide lower gate resistance, improving both DC and RF performance [P3].

Interfaces and Failure Propagation

Si–Gate Oxide Interface

The Si–SiO₂ interface is the most critical interface in the entire transistor [T3]. Long-term operation at high electric fields, especially at elevated temperatures, breaks weaker chemical bonds at this interface, creating oxide charge and causing threshold voltage shift — a primary reliability concern [T3]. Any contamination or damage introduced during the pad oxide remove or gate oxide growth steps directly degrades this interface and propagates into device failure modes including:

• Threshold voltage instability: Charge trapping at interface states causes V_t drift over time, changing circuit behavior [T3].
• Gate leakage increase: Interface defects create additional tunneling paths, increasing off-state power consumption [T3].
• Oxide breakdown: Defect accumulation eventually leads to destructive dielectric breakdown, causing permanent device failure [T3].

Gate Oxide–Gate Electrode Interface

In poly-SiON stacks, the poly-Si–gate oxide interface suffers from the polysilicon depletion effect, which becomes more severe as the gate oxide is scaled thinner [T2]. In HKMG stacks, the high-k–metal gate interface introduces work function tuning challenges: the metal gate work function must be precisely controlled to achieve the desired threshold voltage for both NFET and PFET devices [P2]. Any interdiffusion or reaction between the high-k and metal gate layers during subsequent thermal processing can shift the effective work function and alter V_t [T1].

Downstream Consequences

Defects introduced in the gate stack module propagate downstream in several directional ways:

• LDD and source/drain implant alignment: The gate electrode edge defines the self-aligned boundary for LDD implants [A1]. Any gate CD variation or profile abnormality directly affects the LDD extension length, which in turn controls the overlap capacitance and hot-carrier reliability [P1].
• Sidewall spacer formation: The gate stack sidewall profile determines the spacer shape, which controls the source/drain junction depth and the channel overlap [A2]. A tapered or rough gate sidewall leads to non-uniform spacer formation and junction non-uniformity [P1].
• Silicidation: The gate top surface must be clean and uniform for reliable silicide formation [T1]. Any residue or roughness from gate patterning causes inconsistent silicide phase formation, increasing gate series resistance [P1].

Tradeoffs

The fundamental tradeoff in 28nm gate stack design is between drive current and gate leakage [T3]. Thinner gate oxide (or smaller EOT) increases C_{ox}, raising drive current and improving short-channel control, but exponentially increases tunneling leakage [T3]. The subthreshold swing, which limits how low V_t can be scaled, is proportional to the thermal voltage and the sub-threshold slope factor:

S \propto \eta \frac{kT}{q}

where \eta is the subthreshold slope factor related to the ratio of C_{ox} to junction capacitance [T3]. This thermodynamic limit means that reducing V_t below a certain point necessarily increases off-state leakage exponentially, as described by:

I_{ds} \propto \exp\left(\frac{q V_{gs}}{\eta kT}\right)

The gate stack must therefore achieve an EOT thin enough for adequate short-channel control without pushing tunneling leakage to unacceptable levels — a balance that drove the transition to HKMG at this node [P2][P3].

Walk the Real Module

To see exactly how these principles manifest in a real 28nm planar process flow, you can explore the interactive GATE module sequence [P1]. The Open GATE Step 33 in the interactive flow shows the actual step ordering and module dependencies within the gate stack formation sequence (Engineering Practice).

In this interactive flow, you can trace how the pad oxide remove step transitions the wafer from its post-implant state to a bare silicon surface ready for gate dielectric growth [T1]. The sequence illustrates the tight coupling between the 28nm Planar well formation process flow and the gate stack module: the well and channel implant steps establish the doping profile that the gate dielectric must overlay, and the pad oxide that protected that profile during implantation must be removed before the gate oxide can be grown with the required interface quality [P3].

The interactive flow also demonstrates how the gate stack module's position in the overall sequence — after channel implants, before LDD implants — is a direct consequence of the self-alignment and thermal budget constraints discussed above [T3]. Each step in the sequence has a defined entry state and exit state, and the gate stack module's entry state (bare, implant-damaged silicon protected by pad oxide) and exit state (patterned gate electrode with high-quality gate dielectric) define the boundaries within which the module must operate [A1].

Related Learning Paths

For engineers seeking to deepen their understanding of the 28nm planar process, several adjacent topics provide complementary context:

• 28nm Planar process flow overview: Provides the complete module sequence and shows how the gate stack fits within the broader integration scheme [P1].
• 28nm Planar well and channel implant integration: Details the doping profile engineering that precedes the gate stack and determines the channel characteristics the gate dielectric must overlay [P3].
• 28nm Planar well formation: Explains the retrograde well structures that provide electrostatic confinement for the channel, complementing the gate stack's role in electrostatic control [P3].

Engineers may also wish to explore the FD-SOI variant of the 28nm planar node, where the gate stack interacts with an ultra-thin silicon body and buried oxide rather than a bulk substrate, introducing different constraints on gate dielectric thickness and back-gate coupling [P3][A1].

Future Outlook

The 28nm node represents a pivotal point in planar CMOS evolution [P3]. As noted in the literature, "from the 28 nm node onward, planar CMOS faces challenges in electrostatic control and degradation of analog performance, making FD-SOI and FinFET the two major fully depleted device solutions" [P3]. The gate stack integration principles established at 28nm — including the pad oxide remove, gate oxide growth, and HKMG stack formation — continue to influence subsequent nodes, even as the device architecture transitions from planar to three-dimensional [P1].

Emerging research directions include:

• Gate-all-around (GAA) architectures: Extending the gate-wrapping concept demonstrated in UTBB FDSOI patents to nanosheet and nanowire structures, where the gate dielectric must conform to multiple surfaces [A1][A2].
• Novel high-k materials: Exploring dielectrics with higher permittivity than HfO₂ to further reduce EOT while maintaining leakage control [T2].
• Interface engineering: Developing techniques to minimize the interfacial oxide layer between silicon and high-k, as this layer increasingly dominates the EOT budget at advanced nodes [T3].
• Work function tuning: Advancing metal gate materials and deposition techniques to achieve precise dual-work-function control without thermal budget constraints [P2].

The constant-field scaling theory that underpinned the transition to 28nm — proportionally reducing channel length, gate oxide thickness, and threshold-adjustment dose to maintain controlled electric fields [P1] — remains a guiding principle, even as new device architectures and materials extend its applicability beyond the planar regime.