28nm Planar Gate Stack Integration Process Flow: Principles, Mechanisms, and Integration Logic

Role in the Complete Flow

The 28nm planar gate stack integration is one of the most critical modules in the entire 28nm Planar process flow, sitting at the intersection of channel electrostatic engineering and source/drain formation. Upstream, this module receives a wafer that has already completed shallow trench isolation (STI), well formation, channel implantation, and threshold-voltage adjustment implants. In front-end integration, after the formation of shallow trench isolations, well implantations and channel implantations are completed before gate dielectric and gate electrode formation [P2]. The active silicon surface is protected by a sacrificial or pad oxide layer that served as a screen during ion implantation steps and as a protective barrier during cleaning operations. The gate stack module must transform this surface into a high-quality gate dielectric and electrode stack that defines the transistor threshold voltage, drive current, off-state leakage, and long-term operating reliability.

Downstream, the gate stack delivers a patterned gate electrode that acts as a self-aligned mask for lightly doped drain (LDD) implants, sidewall spacer formation, and source/drain implantation. Any defect, thickness non-uniformity, or interface contamination introduced in this module propagates directly into downstream electrical characteristics. The gate oxide capacitance per unit area directly controls the threshold voltage through the relationship V_t = V_FB + ϕ_s + Q_d / C_ox, where C_ox is inversely proportional to the gate dielectric equivalent oxide thickness (EOT). A thinner gate dielectric raises C_ox, improving drive current and suppressing short-channel effects, but also increases gate tunneling leakage exponentially. To address scaling limitations, the use of high dielectric constant (high-k) materials as the replacement of SiO2 is expected to maintain gate capacitance density and obtain greater physical thickness, effectively leading to the suppressed leakage current [P4].

At the 28nm node, dual-gate oxide schemes (for core low-voltage logic and I/O high-voltage transistors) and high-k metal gate (HKMG) stacks are integrated to meet diverse power and performance constraints. The choice between gate-first and replacement gate (gate-last) integration schemes profoundly affects how the gate stack module interacts with thermal budgets and subsequent process steps.

Entry State and Sequence Logic

What the Module Receives

When the GATE module process flow begins, the wafer carries a completed STI structure and a defined channel doping profile established through well and channel implants. The active silicon surface is covered by a pad oxide grown or deposited earlier in the flow. This pad oxide is not suitable as a device gate dielectric: it has been exposed to implant damage and potential contamination, and its thickness was chosen for implant screening rather than dielectric reliability.

The 28nm Planar well and channel implant integration process flow establishes the retrograde well profiles and threshold-adjustment implants that determine channel doping. The surface silicon quality beneath the pad oxide is critical: any crystal damage, metallic contamination, or particulate residue from upstream steps will degrade gate dielectric breakdown strength and shift threshold voltages.

Sequence Dependencies

The gate stack must be formed after channel implants are complete but before LDD and source/drain implants. This ordering is dictated by two competing constraints:

1. Thermal budget: Gate dielectric growth and high-k post-deposition anneals must occur after channel implants so that doping profiles are stabilized, but before high-temperature source/drain activation anneals, as excessive thermal exposure after gate dielectric formation can induce material interdiffusion and degrade interface quality.

2. Self-alignment: The gate electrode serves as the self-aligned hard mask for LDD and source/drain implants. If the gate were patterned before channel implant completion, the channel doping profile under the gate edges would become non-uniform.

In gate-first HKMG integration, the high-k dielectric and metal gate layers are deposited before source/drain formation and must survive subsequent thermal activation budgets. In contrast, replacement gate approaches use a dummy polysilicon gate during front-end processing and replace it with the final metal gate stack after high-temperature steps, decoupling gate materials from thermal activation constraints at the cost of additional integration complexity.

Physical and Chemical Mechanisms

Pad Oxide Removal and Dual Gate Oxide Integration

A foundational step in the gate stack module is pad oxide removal. The existing oxide contains implant defects and surface contamination. Dilute hydrofluoric acid (DHF) is used to strip the pad oxide prior to gate dielectric growth. The wet chemical etch proceeds via the reaction:

SiO₂ + 6HF → H₂SiF₆ + 2H₂O

DHF exhibits high chemical selectivity when etching silicon dioxide over crystalline silicon. However, because the etch is unmasked, it also etches field oxide surfaces (STI) concurrently. The process timing is carefully optimized to strip the pad oxide thoroughly while minimizing field oxide recessing.

In dual-gate integration, thick gate oxide for I/O transistors is grown first, followed by dual-gate photolithographic patterning, photoresist trimming, and selective etching of the thick oxide from core device areas. A second oxidation step then forms the thin gate oxide in core transistor regions, establishing two distinct dielectric thickness regimes on the same substrate.

High-k Dielectric and Interfacial Layer Growth

An interfacial silicon oxide layer is maintained beneath the high-k film to avoid the adverse effects of possible large density of interface defects at the high-k/Si-channel interface to be resulted from the large lattice mismatching between the Si and high-k gate dielectric [P3]. This interfacial oxide is subjected to pre-cleans and surface treatments, such as plasma nitridation, to enhance dielectric reliability and prevent dopant penetration.

Following interfacial layer preparation, a high-k dielectric layer such as hafnium oxide (HfO₂) is deposited by atomic layer deposition (ALD). The EOT of the stacked gate dielectric is defined by:

EOT = t_interfacial + t_high-k × (K_SiO₂ / K_high-k)

where t_high-k is the physical thickness of the high-k layer, and K values represent relative dielectric constants. Because K_high-k is significantly higher than K_SiO₂, the stack achieves a low EOT while preserving physical thickness to limit direct tunneling leakage. Post-deposition anneals (PDA) and post-nitridation anneals (PNA) are then applied to densify the high-k film and passivate oxygen vacancies.

Gate Electrode Deposition and Patterning

In HKMG stacks, a thin metal gate layer such as TiN is deposited directly above the high-k dielectric to set the effective gate work function and eliminate polysilicon depletion effects. An amorphous silicon or polysilicon layer is deposited over the metal gate to protect the stack and serve as a sacrificial or structural capping electrode.

Patterning the gate stack requires a multi-layer hard mask approach. Hard mask films—including silicon nitride, silicon oxide, amorphous carbon, and nitrogen-free DARC—are deposited sequentially. Photolithography defines the gate critical dimension (CD), which is transferred into the hard mask and underlying poly/metal/high-k layers through selective plasma etching.

Interfaces and Failure Propagation

Si–Dielectric and High-k–Metal Interfaces

The Si–SiO₂ interfacial layer is sensitive to surface roughness and contamination. Long-term electric field stress can break weak chemical bonds at this interface, creating interface traps and fixed charges that cause threshold voltage drift.

At the high-k/metal gate interface, interdiffusion or phase instability during thermal processing can alter the effective work function, resulting in threshold voltage shifts between n-channel and p-channel transistors.

Downstream Consequences

Defects or dimensional variations in the gate stack propagate into subsequent modules:

• LDD and source/drain alignment: Gate CD variation or tapered sidewalls alter the self-aligned boundary for LDD implants, directly shifting overlap capacitance and short-channel control.
• Sidewall spacer geometry: Asymmetric gate sidewalls cause non-uniform spacer deposition and etching, altering source/drain junction offsets.
• Silicidation: Poly gate top contamination prevents uniform silicide formation, increasing gate contact series resistance.

Performance and Leakage Tradeoffs

The core tradeoff in gate stack scaling is between drive current and off-state gate leakage. The subthreshold swing S is limited by thermal voltage and electrostatics:

S ∝ η × (kT / q)

where η is the subthreshold slope factor related to gate dielectric and depletion capacitances. Reducing V_t to increase drive current increases subthreshold leakage exponentially according to:

I_ds ∝ exp(q × V_gs / (η × kT))

The gate stack must optimize EOT and work function alignment to achieve targeted drive current without exceeding off-state power limits.

Walk the Real Module

To trace how these mechanisms operate within a 28nm flow, explore the Pad Oxide Remove for Thick Gate in the interactive flow. This step marks the transition from post-implant surface preparation to gate dielectric formation.

The module illustrates how upstream doping profiles established in the 28nm Planar well formation process flow dictate the clean and oxidation parameters required for reliable interface formation.

Related Learning Paths

• 28nm Planar process flow overview: Complete module architecture and sequence logic across the full integration.
• 28nm Planar well and channel implant integration: Channel doping engineering preceding gate stack formation.
• 28nm Planar well formation: Retrograde well construction and isolation boundaries.

Future Outlook

The 28nm node represents the climax of high-volume planar CMOS scaling. Beyond 28nm, electrostatic short-channel degradation accelerated the adoption of FD-SOI and 3D FinFET architectures. However, the foundational physics of HKMG stack design, interfacial layer passivation, and multi-layer gate lithography established at 28nm continue to underpin advanced gate-all-around (GAA) nanosheet devices.