28nm Metal Gate CMP Mechanism: Principles, Dishing Control, and Integration Logic

Function in the Complete Flow

In advanced planar CMOS technology, the replacement metal gate (RMG) integration scheme was introduced to preserve high-k gate dielectric integrity by eliminating high-temperature anneals after metal gate deposition [P2, P3]. Within the 28nm replacement metal gate integration, Chemical Mechanical Polishing (CMP)—often referred to as Metal Gate CMP or MG CMP—serves as the critical unit operation that isolates individual metal gate electrodes across the wafer [P1, P3].

The MG CMP step receives a wafer covered in a continuous metal overburden after work-function metal and bulk fill metal (typically aluminum in ALCMP processes or tungsten) have been deposited into narrow gate trenches [P1, A1]. The objective of this operation is to mechanically and chemically remove the overburden metal while stopping abruptly on the surrounding dielectric material or sidewall spacers, which act as the metal gate CMP stop layer [P1, A1].

Once completed, the process hands off an array of electrically isolated, co-planar metal gates embedded within the inter-layer dielectric (ILD) matrix [P1, P2]. This planarized topography is critical for subsequent contact lithography and metallization steps, where any residual metal overburden would cause severe inter-gate electrical shorting, while excessive over-polishing would lead to unrecoverable gate height degradation [P1, P2]. For a broader perspective on how this module fits into the overall manufacturing sequence, explore the 28nm Planar process flow [P1].

Upstream Input State

Prior to the replacement metal gate planarization 28nm step, the wafer undergoes complex structural transformations that establish the incoming surface state [P1, P2]. First, the dummy polysilicon gates are exposed via a Poly-Open-Polish (POP) CMP step, which planarizes the primary dielectric layer down to the top of the dummy structures [P1, P3]. These dummy polysilicon gates are subsequently removed using selective wet and dry chemical etches, leaving high-aspect-ratio trenches bounded by silicon nitride or oxide sidewall spacers [P1, A1].

Following dummy gate removal, an ultra-thin high-k gate dielectric (such as hafnium oxide) and thin work-function metal stacks (including titanium nitride and titanium carbide) are conformally liner-deposited into the narrow trenches [P1, A1]. Finally, bulk gate metal—most commonly low-resistance aluminum—is deposited to fully fill the gate cavities [P1, A1].

Because bulk deposition processes must ensure total fill of dense, narrow features without void formation, a substantial, non-uniform metal overburden remains across the entire wafer surface [P1, T2]. The incoming profile presents severe micro-topography, featuring deep topography steps between high-density gate areas and isolated regions [P1]. This incoming non-uniformity makes metal gate CMP dishing and metal height control the primary technical challenge inherited by the CMP module [P1, P2].

Physical and Chemical Mechanisms

The fundamental mechanism of Metal Gate CMP relies on a synergistic balance between surface chemical oxidation/passivation and mechanical abrasive shear force [P1, T1]. Unlike oxide CMP, which depends heavily on surface hydration kinetics, metal gate removal requires chemical transformation of the bulk metal into a softer, chemically modified surface layer that can be abraded by slurry particles without aggressive mechanical damage to the underlying substrate [T1, P3].

  Slurry Hydrodynamics & Mechanical Shear
               │
               ▼
┌─────────────────────────────┐
│ Softened Metal Oxide Layer  │  ◄── Chemical Oxidizer & Passivator
├─────────────────────────────┤
│   Bulk Metal Gate Fill      │
└─────────────────────────────┘

During polishing, chemical components in the slurry—specifically oxidizers, chelating agents, and organic corrosion inhibitors—react dynamically with the metal surface [P3, T1]. The oxidizer converts the top atomic layers of the bulk metal into a metal oxide or complexed hydroxyl compound, which exhibits significantly lower mechanical hardness than the unreacted metal [P3, T1]. Simultaneously, organic passivating agents selectively adsorb onto low-recessed areas, protecting them from chemical etching while high-pressure pad-particle contacts mechanically shear away the passivated oxide layer on elevated features [P3, T1].

The mechanical removal rate is dictated by dynamic contact mechanics between the polyurethane polishing pad, colloidal silica abrasives, and the wafer surface [P1, T1]. As the metal overburden is cleared and the underlying dielectric or sidewall spacer is exposed, the removal chemistry must exhibit high selectivity [P3, A1]. The sidewall spacers and oxide matrix act as a metal gate CMP stop layer, causing the polishing rate to drop dramatically once the metal overburden is consumed [P1, A1].

However, because the metal fill in the gate trench is chemically softer and subjected to differential slurry flow compared to the surrounding hard dielectric, localized over-polishing causes recessed erosion known as dishing [P1]. Control of dishing depends directly on pattern density [P1]. High-coverage metal regions experience locally altered pad contact pressure and slurry delivery, increasing susceptibility to erosion, whereas isolated metal gates risk dishing if chemical passivation is insufficient [P1]. To mitigate these pattern-dependent loading effects, layout design rules enforce dummy poly and metal fill insertion across the chip to maintain uniform local pattern density and mechanical load distribution [P1].

Downstream Impact and Failure Propagation

Imbalances in the physical or chemical kinetics of the 28nm replacement metal gate integration CMP step propagate directly into device performance and yield loss downstream [P1, P2]. The primary parameters governed by this step are final metal gate height, gate-to-gate isolation, and cross-wafer gate height uniformity [P1, P2].

                    ┌──► Excessive Dishing ──► Gate Height Loss ──► Threshold Voltage Shift & Resistance Variation
                    │
MG CMP Imbalance ───┼──► Under-Polishing  ──► Residual Overburden ──► Gate-to-Gate Short Circuit
                    │
                    └──► Dielectric Erosion ─► Spacer Recess ──────► Contact-to-Gate Leakage

If chemical etching dominates over mechanical passivation, severe metal gate CMP dishing occurs, resulting in unrecoverable metal gate height loss [P1]. Reduced gate height directly alters the cross-sectional area of the gate electrode, elevating gate line resistance and inducing threshold voltage variability across different functional blocks [P1, P2]. Furthermore, excessive dishing or dielectric erosion degrades the surface margin required for subsequent dielectric cap deposition and contact hole etching [P1, A1]. During downstream contact formation, eroded spacers can cause the contact etch to pierce into adjacent gate electrodes, creating catastrophic gate-to-contact shorts [P1, A1].

Conversely, insufficient polishing or low slurry removal rates leave micro-residues of work-function metal or bulk overburden across the field dielectric [P1, P3]. These residual conductive films bridge adjacent transistor gates, leading to widespread short circuits and total functional failure of the integrated circuit [P1]. Achieving precise metal gate CMP dishing and metal height control is therefore essential to preserving the tight process window required for low-power and high-performance CMOS logic devices [P1]. For a detailed operational breakdown of gate replacement, see the 28nm Planar replacement metal gate integration process flow [P3].

Walk the Real Step

To see where this specific unit operation is executed within the full manufacturing sequence, inspect the verified process step link below:

Open RMG Step 167 in the interactive flow

This step isolates the metal gate stack by removing overburden metal while stopping cleanly on the surrounding dielectric structures to lock in transistor channel properties [P3].

Related Learning Paths

To deepen your understanding of adjacent modules in advanced planar CMOS fabrication, explore the following dedicated process guides:

• 28nm Planar Process Flow: Integration Logic, Device Physics, and Module Dependencies — Overview of the overall module architecture, front-end-of-line isolation, and back-end integration rules [T2].
• 28nm Planar Replacement Metal Gate Integration Process Flow: Principles, Mechanisms, and Integration Logic — Deep dive into dummy gate removal, high-k deposition, work-function tuning, and gate fill modules [P3].

Future Outlook

As technology scaling advanced beyond the 28nm planar node into 3D FinFET and gate-all-around architectures, the fundamental principles of MG CMP evolved to address even tighter dimensional tolerances [P1]. Higher aspect ratio gate trenches and multi-threshold-voltage work function metal stacks demand sub-nanometer planarity and near-zero dishing across complex 3D topographies [P1, P2].

Recent research explores advanced material modification techniques to dynamically alter CMP slurry response [P2]. For instance, ultra-high-dose carbon ion implantation into dielectric materials has been shown to alter surface bonding and chemical reactivity, drastically reducing oxide removal rates and significantly boosting CMP selectivity during gate-last operations [P2]. In addition, self-assembling passivating monolayers and highly tunable chemical additives are being developed to refine ALCMP and tungsten polish steps, ensuring that extreme gate height uniformity can be maintained in future quantum and ultra-dense logic generations [P2, P3].