28nm Metal Gate CMP Mechanism: Principles, Dishing Control, and Integration Logic

Function in the Complete Flow

In advanced planar CMOS technology, the replacement metal gate (RMG) integration scheme was introduced to preserve high-k gate dielectric integrity by eliminating high-temperature thermal processing after metal gate stack deposition. Within 28nm replacement metal gate integration, Chemical Mechanical Polishing (CMP)—commonly referred to as Metal Gate CMP (MG CMP)—serves as the primary unit operation that isolates individual metal gate electrodes across the wafer surface.

The MG CMP step receives a wafer covered in a continuous metal overburden after work-function metal layers and bulk fill metal (such as aluminum or tungsten) have been deposited into narrow gate trenches. A CMP process is further implemented to polish and remove the excessive gate materials from the semiconductor structure . The objective of this operation is to mechanically and chemically remove the overburden metal while stopping on the surrounding dielectric material or sidewall spacers, which act as the metal gate CMP stop layer.

Once completed, the process hands off an array of electrically isolated, co-planar metal gates embedded within the inter-layer dielectric (ILD) matrix. This planarized topography is critical for subsequent contact lithography and metallization steps, where any residual metal overburden would cause severe inter-gate electrical shorting, while excessive over-polishing would lead to unrecoverable gate height degradation. For a broader perspective on how this module fits into the overall manufacturing sequence, explore the 28nm Planar process flow.

Upstream Input State

Prior to the metal gate planarization step, the wafer undergoes structural transformations that establish the incoming surface state. First, dummy polysilicon gates are exposed via a CMP planarization step down to the top of the dummy structures. These dummy polysilicon gates are subsequently removed using selective chemical etches, leaving high-aspect-ratio trenches bounded by silicon nitride or oxide sidewall spacers.

Following dummy gate removal, an ultra-thin high-k gate dielectric (such as hafnium oxide, HfO2) and thin work-function metal stacks (including titanium nitride, TiN, and titanium aluminide, TiAl) are conformally liner-deposited into the narrow trenches. Finally, bulk gate metal—most commonly low-resistance aluminum or tungsten—is deposited to fully fill the gate cavities.

Because bulk deposition processes must ensure complete fill of dense, narrow features without void formation, a substantial metal overburden remains across the wafer surface. The incoming profile presents severe micro-topography, featuring deep topography steps between high-density gate areas and isolated dielectric field regions. Managing this incoming non-uniformity makes dishing and metal height control the primary technical challenges inherited by the CMP module.

Physical and Chemical Mechanisms

CMP is a global planarization process in which the wafer surface is planarized using the synergistic effect of chemical and mechanical actions [P2]. For metal removal, the solution oxidizes the surface which is then polished in a similar fashion to oxide removal [T1]. In general, a metal CMP slurry contains chemical oxidizers, complexing agents, and corrosion inhibitors to regulate removal rates.

  Slurry Hydrodynamics & Mechanical Shear
               │
               ▼
┌─────────────────────────────┐
│ Softened Metal Oxide Layer  │  ◄── Chemical Oxidizer & Passivator
├─────────────────────────────┤
│   Bulk Metal Gate Fill      │
└─────────────────────────────┘

The slurry oxidizer converts the top atomic layers of the bulk metal into a metal oxide or complexed compound exhibiting lower mechanical hardness than the unreacted bulk metal. Simultaneously, organic corrosion inhibitors selectively adsorb onto low-recessed areas, protecting them from chemical etching while high-pressure pad-particle contacts mechanically shear away the passivated oxide layer on elevated features.

The mechanical removal rate is dictated by dynamic contact mechanics between the polyurethane polishing pad, colloidal silica or alumina abrasives, and the wafer surface. As the metal overburden is cleared and the underlying dielectric or sidewall spacer is exposed, the removal chemistry exhibits selectivity toward the metal. The sidewall spacers and dielectric matrix act as a stop layer, causing the polishing rate to drop once the metal overburden is consumed.

However, because the metal fill in the gate trench is chemically softer and subjected to differential slurry flow compared to the surrounding hard dielectric, localized over-polishing causes recessed erosion known as dishing. Local thickness variation across different pattern widths and pitches represents a major CMP pattern density effect. High-coverage metal regions experience locally altered pad contact pressure and slurry delivery, increasing susceptibility to erosion, whereas isolated metal gates risk dishing if chemical passivation is insufficient. To mitigate these pattern-dependent loading effects, layout design rules enforce dummy poly and metal fill insertion across the chip to maintain uniform local pattern density and mechanical load distribution.

Downstream Impact and Failure Propagation

Imbalances in the physical or chemical kinetics of the replacement metal gate CMP step propagate directly into device performance and yield loss downstream. The primary parameters governed by this step are final metal gate height, gate-to-gate electrical isolation, and cross-wafer gate height uniformity.

                    ┌──► Excessive Dishing ──► Gate Height Loss ──► Threshold Voltage Shift & Resistance Variation
                    │
MG CMP Imbalance ───┼──► Under-Polishing  ──► Residual Overburden ──► Gate-to-Gate Short Circuit
                    │
                    └──► Dielectric Erosion ─► Spacer Recess ──────► Contact-to-Gate Leakage

If chemical etching dominates over mechanical passivation, severe dishing occurs, resulting in unrecoverable metal gate height loss. Reduced gate height directly alters the cross-sectional area of the gate electrode, elevating gate line resistance and inducing threshold voltage variability across different functional blocks. Furthermore, excessive dishing or dielectric erosion degrades the surface margin required for subsequent dielectric cap deposition and contact hole etching. During downstream contact formation, eroded spacers can cause the contact etch to pierce into adjacent gate electrodes, creating catastrophic gate-to-contact shorts.

Conversely, insufficient polishing or low slurry removal rates leave micro-residues of work-function metal or bulk overburden across the field dielectric. These residual conductive films bridge adjacent transistor gates, leading to widespread short circuits and total functional failure of the integrated circuit. Achieving precise dishing and metal height control is therefore essential to preserving the tight process window required for low-power and high-performance CMOS logic devices. For a detailed operational breakdown of gate replacement, see the 28nm Planar replacement metal gate integration process flow.

Walk the Real Step

To see where this specific unit operation is executed within the full manufacturing sequence, inspect the verified process step link below:

Open RMG Step 167 in the interactive flow

This step isolates the metal gate stack by removing overburden metal while stopping cleanly on the surrounding dielectric structures to lock in transistor channel properties.

Related Learning Paths

To deepen your understanding of adjacent modules in advanced planar CMOS fabrication, explore the following dedicated process guides:

• 28nm Planar Process Flow: Integration Logic, Device Physics, and Module Dependencies — Overview of the overall module architecture, front-end-of-line isolation, and back-end integration rules.
• 28nm Planar Replacement Metal Gate Integration Process Flow: Principles, Mechanisms, and Integration Logic — Deep dive into dummy gate removal, high-k deposition, work-function tuning, and gate fill modules.

Future Outlook

As technology scaling advanced beyond planar architectures into 3D FinFET and gate-all-around devices, the fundamental principles of MG CMP evolved to address tighter dimensional tolerances. Higher aspect ratio gate trenches and multi-threshold-voltage work function metal stacks demand nanometer-scale planarity and tight dishing control across complex 3D topographies.

Recent process innovations focus on advanced slurry formulations and surface passivating additives to dynamically alter CMP response. Self-assembling passivating monolayers and highly tunable chemical additives refine aluminum and tungsten polish steps, ensuring that tight gate height uniformity can be maintained across diverse logic layout patterns.