Function in the Complete Flow
In modern image sensor manufacturing, backside illuminated (BSI) architectures have replaced conventional frontside illuminated configurations to maximize optical fill factor and eliminate light blockage from multi-level interconnect metal layers . In a 40nm BSI CMOS Image Sensor (CIS) flow, the silicon substrate containing the active photodiode array and readout circuitry is inverted and bonded to a handle wafer via oxide-to-oxide or hybrid metal-dielectric direct bonding , . Following hybrid bonding, the original silicon donor substrate must undergo severe backside thickness reduction so light can directly enter the underlying pinned photodiodes .
The two-stage backside silicon chemical mechanical planarization (CMP) process, designated as Step 296 in the module flow, represents the central bridge between initial coarse mechanical grinding and downstream backside surface processing , . Located within the 40nm BSI CMOS Image Sensor backside wafer thinning process flow, this dual-stage precision CMP module receives a roughly thinned wafer containing significant subsurface mechanical damage and macro-scale thickness non-uniformities , . The primary function of Step 296 is to transition the backside surface from a rough, damaged silicon state to an optically flat, lattice-pristine, nanometer-thin silicon membrane while maintaining strict total thickness variation (TTV) control , .
Once this two-stage backside silicon CMP step is complete, the wafer is handed off to downstream steps within the primary 40nm BSI CMOS Image Sensor process flow, including surface passivation, anti-reflective coating (ARC) deposition, backside trench isolation, and the formation of color filter arrays and microlenses . Without precise execution at this junction, residual crystal damage or thickness non-uniformities directly degrade sensor electro-optical parameters, such as dark current and quantum efficiency .
Guided route
CIS Backside Si, CMP2 (target thickness adjust)
This article maps to Chapter 4 (Thinning) of the 40nm BSI structural spine — 6 stops through the complete flow, each with rationale and 2.5D cross-section evolution.
- 1Isolation
- 2Photosensitive junction
- 3Bonding
- 4ThinningThis article
- 5Color selection
- 6Light focusing
Upstream Input State
Before entering the two-stage backside silicon CMP module, the wafer stack undergoes several mechanical, thermal, and chemical operations that leave distinct structural and surface signatures , :
- Wafer Bonding Strain and Bow: The device wafer is bonded face-to-face to a supporting carrier or handle wafer . Differences in thermal expansion coefficients between multi-layer interconnect dielectrics, embedded metal lines, and silicon substrates generate internal stress, causing overall wafer warp and localized bowing , .
- Subsurface Damage (SSD): Prior mechanical grinding steps rapidly remove the bulk of the donor silicon wafer . However, aggressive diamond-grit abrasive interaction leaves micro-fractures, dislocation loops, and severe crystal lattice disturbance extending below the ground silicon surface .
- Macro-Scale Total Thickness Variation (TTV): Coarse mechanical thinning exhibits high material removal rates but exhibits intrinsic spatial non-uniformities . The incoming substrate presents a non-uniform profile, such as a dome-shaped or edge-fast thickness distribution across the wafer diameter .
- Edge Roll-Off and Topography: Edge trimming operations executed before back grinding prevent wafer edge chipping during thinning . This leaves a step-height boundary near the wafer perimeter, accompanied by localized stress concentrations and slurry fluid dynamic variations during subsequent CMP handling , .
The two-stage CMP process must systematically absorb these incoming structural non-uniformities, strip away the subsurface damage zone, and re-establish a flat plane parallel to the internal photodiode array , .
Physical and Chemical Mechanisms
The 40nm BSI CIS thinning mechanism relies on a dynamic synergy between surface oxidation kinetics, mechanical shear forces, and optical metrology control , . The two-stage CMP approach decouples the competing requirements of high material removal rate (MRR) and atomic-scale surface defectivity control .
Incoming Ground Wafer (High Roughness & Subsurface Damage)
│
▼
┌────────────────────────────────────────────────────────┐
│ Stage 1: Bulk Silicon Thinning & Planarization │
│ • Alkaline oxidation-softening chemistry │
│ • High-downforce mechanical abrasive shearing │
│ • Multi-zone carrier pressure compensates macro-TTV │
└────────────────────────────────────────────────────────┘
│
▼
┌────────────────────────────────────────────────────────┐
│ Stage 2: Fine Polish & Damage Removal │
│ • Low-stress silica/ceria colloidal slurry │
│ • Removal of residual micro-cracks & dislocations │
│ • Sub-nanometer surface roughness (Ra) stabilization │
└────────────────────────────────────────────────────────┘
│
▼
┌────────────────────────────────────────────────────────┐
│ Real-Time Optical Metrology & Endpoint Control │
│ • In-situ interferometric / spectral reflectivity │
│ • Multi-zone pressure/thermal closed-loop control │
└────────────────────────────────────────────────────────┘
│
▼
Pragmatic Backside Silicon Surface Ready for Passivation & Lithography
Stage 1: Bulk Silicon Thinning and Macro-Planarization
The first CMP stage targets high removal rates to eliminate the bulk of residual silicon above the active photodiodes and level macro-scale surface height variations .
- Chemical Oxidation-Softening: The Stage 1 slurry features an alkaline chemical formulation (elevated pH) that reacts with the elemental silicon surface , . Hydroxide ions attack the silicon lattice, forming a softened, hydrated silicon dioxide interface layer .
- Mechanical Abrasive Shearing: Polymeric polishing pads combined with sub-micron abrasive particles apply downforce and relative velocity to shear away the newly formed softened oxide layer . According to contact mechanics models, material removal occurs dynamically: chemical reactions continuously hydrate the top atomic monolayers, while mechanical contact removes the softened material .
- Multi-Zone Force Control: To correct the inherited dome-shaped or spatial TTV profile from back grinding, the polishing head employs independently pressurized concentric zones . Higher pneumatic back-pressure is directed to thicker wafer regions to increase local mechanical removal rates, flattening the macro-profile , .
Stage 2: Fine Polish, Damage Elimination, and Micro-Planarization
Once Stage 1 brings the silicon membrane near its operational thickness window, Stage 2 transitions to a low-stress, defect-minimizing regime .
- Subsurface Damage Elimination: The primary objective of Stage 2 is to gently remove the remaining crystalline dislocation networks created by mechanical grinding without introducing new polishing scratches .
- Slurry Chem-Mechanics: Stage 2 utilizes ultra-fine colloidal silica or ceria particles suspended in a passivating chemistry . Chemical etching kinetics are balanced to suppress micro-pitting, while low mechanical downforce prevents abrasive scratching and micro-chipping .
- Surface Roughness Minimization: This stage lowers average surface roughness ($R_a$) down to sub-nanometer levels, establishing an optically smooth surface required for high-transmission anti-reflective coatings and precise optical lithography , .
In-Situ Metrology and Endpoint Detection
Achieving reliable backside silicon thickness control requires real-time monitoring during polishing .
- Interferometric Spectral Reflectance: Broad-spectrum or monochromatic light is directed through the polishing pad window onto the wafer backside , . Reflected light waves from the upper air/silicon interface and the underlying silicon/dielectric interface interfere with one another , .
- Thin-Film Interference Interference Model: The spectral reflectivity $R$ depends on film thickness $d$, refractive index $n$, and incident optical phase $\beta$, described qualitatively by:
$$\beta = \frac{2\pi \cdot n \cdot d}{\lambda}$$
As the silicon thins, the phase shift changes periodically, generating sinusoidal interference signals , . Algorithms process these spectral fringes in real time to calculate remaining silicon thickness, dynamically triggering polishing stop commands when the targeted silicon membrane thickness is reached , .
Downstream Impact and Failure Propagation
Process variations or marginalities during the two-stage backside silicon CMP step propagate directly into downstream module performance and overall chip yield , :
+------------------------------------+---------------------------------------------------+---------------------------------------------------------+
| CMP Defect / Non-Uniformity | Direct Physical Consequence | Downstream Device Failure Mode |
+------------------------------------+---------------------------------------------------+---------------------------------------------------------+
| Silicon Thickness Non-Uniformity | Spatial variation in optical absorption path | Pixel-to-pixel quantum efficiency variations & color |
| (High TTV / LTV) | length across the array | crosstalk *(Engineering Practice)* |
+------------------------------------+---------------------------------------------------+---------------------------------------------------------+
| Unremoved Subsurface Damage (SSD) | High density of lattice dislocations & traps | Elevated dark current, hot pixels, and excessive dark |
| | in active silicon | random noise *(Engineering Practice)* |
+------------------------------------+---------------------------------------------------+---------------------------------------------------------+
| High Surface Micro-Roughness | Scattering of incident photons at backside | Decreased total light transmission and reduced peak |
| | silicon surface | sensitivity *(Engineering Practice)* |
+------------------------------------+---------------------------------------------------+---------------------------------------------------------+
| Localized Over-Polishing / | Penetration or erosion into active photodiode | Complete pixel deadness, shorting, or catastrophic yield |
| Punch-Through | structures | loss [A2] |
+------------------------------------+---------------------------------------------------+---------------------------------------------------------+
| Excessive Shear Stress | Mechanical strain propagated to bonding interface | Interfacial delamination or bond-pad micro-cracking |
| | | [A1], [A4] |
+------------------------------------+---------------------------------------------------+---------------------------------------------------------+
Optical Transmission and Quantum Efficiency
Silicon exhibits a finite optical absorption depth dependent on photon energy (Engineering Practice). If backside silicon thickness control fails, non-uniform silicon thickness across the photodiode array causes localized variations in light absorption . Thicker silicon regions absorb short-wavelength light before photons reach the active charge collection zone, reducing sensitivity, whereas excessively thinned regions allow long-wavelength light to pass entirely through the active layer, resulting in red/near-infrared response loss .
Dark Current and White Pixels
Subsurface mechanical damage acts as a high-density sink for metallic impurities and generates mid-gap state traps within the bandgap . If Stage 2 CMP fails to completely remove damaged lattice layers, thermally generated electron-hole pairs flow into the photodiode storage nodes even in complete darkness . This manifests downstream as high dark current, dark current shot noise, and localized "white pixel" defects that degrade image quality in low-light environments (Engineering Practice).
Lithographic Focal Depth Limits
Subsequent manufacturing steps involve photolithography to pattern backside deep trench isolation (BDTI), color filter grids, and micro-lens arrays . Photolithography scanners require an extremely flat focal plane . High local thickness variation (LTV) or severe edge roll-off distorts the local image plane beyond the scanner's depth of focus, leading to pattern bridge formation, line-width variation, or misaligned color filter structures , .
Walk the Real Step
In the operational 40nm BSI CIS manufacturing sequence, the execution of this dual-stage process requires precise synchronization between head kinematics, slurry flow state, and in-situ metrology feedback , .
To explore where this operation sits within the interactive manufacturing sequence, view the detailed step documentation:
During process execution at Step 296, the bonded wafer is loaded onto a multi-zone carrier head face-down against a polyurethane polishing pad . Stage 1 high-rate slurry is introduced to quickly eliminate back-grinding surface damage while multi-zone carrier pressure profiles adjust dynamically to eliminate macro-TTV , . As the integrated optical metrology system detects the approaching target thickness, the tool automatically switches platens or slurry feeds to Stage 2 chemistry , . Stage 2 lowers the downforce to perform a gentle polish, removing microscopic scratch defects and stabilizing the silicon surface prior to post-CMP chemical cleaning .
Related Learning Paths
To further understand how backside wafer thinning interacts with adjacent integration modules in advanced image sensors, explore these process flow articles:
- 40nm BSI CMOS Image Sensor process flow: A comprehensive overview of the end-to-end manufacturing sequence, from frontside pixel fabrication and hybrid bonding to backside processing and module completion .
- 40nm BSI CMOS Image Sensor backside wafer thinning process flow: A detailed examination of the complete thinning module, covering edge trimming, coarse mechanical grinding, dual-stage CMP, selective wet etching, and surface passivation .
Future Outlook
As BSI technology scales to sub-micron pixel pitches and multi-layer 3D stacked image sensors, traditional two-stage backside CMP faces tighter process window constraints , . Advanced thinning developments focus on several key innovations:
- Integrated CMP and Compensatory Etching: Coupling CMP tools directly with downstream selective dry or wet etching systems . High-resolution post-CMP thickness maps feed forward to localized plasma etching systems, which use micro-zone thermal field control or variable edge-ring height adjustments to compensate for residual CMP non-uniformity .
- Multi-Wavelength In-Situ Spectral Profiling: Upgrading optical endpoint systems from single-wavelength interferometers to advanced broadband spectral matching , . This enables real-time extraction of both silicon membrane thickness and complex multilayer dielectric interfaces despite slurry turbidity and light diffraction caused by underlying pixel layouts , .
- Atomic-Scale Selective Chemical Stops: Transitioning from timed or optical polishing control to self-limiting chemical polishing chemistries that automatically stop on embedded boron-doped silicon epitaxial layers or buried oxide interfaces, ensuring absolute thickness uniformity across full 300mm wafers .