Two-Stage Backside Silicon CMP in BSI Image Sensors: Physics, Integration, and Thickness Control

Function in the Complete Flow

In modern image sensor manufacturing, backside illuminated (BSI) architectures have replaced conventional frontside illuminated configurations to maximize optical fill factor and eliminate light blockage from multi-level interconnect metal layers. In a 40nm BSI CMOS Image Sensor (CIS) flow, the silicon substrate containing the active photodiode array and readout circuitry is inverted and bonded to a carrier or handle wafer via oxide-to-oxide or hybrid metal-dielectric direct bonding. Following hybrid bonding, the original donor silicon substrate must undergo severe backside thickness reduction so incident light can enter the underlying pinned photodiodes directly.

In substrate thinning applications, a combination of lapping or mechanical grinding and chemical-mechanical polishing is often used to thin the silicon layer [T1]. The two-stage backside silicon chemical mechanical planarization (CMP) process serves as the bridge between coarse mechanical grinding and downstream backside surface processing. Located within the 40nm BSI CMOS Image Sensor backside wafer thinning process flow, this dual-stage precision CMP module receives a roughly thinned wafer containing significant subsurface mechanical damage and macro-scale thickness non-uniformities. The primary function of the initial CMP1 stage is to remove the severe dislocation networks and deep micro-cracks left by mechanical grinding, while the secondary CMP2 step—CIS Backside Si, CMP2 (target thickness adjust)—acts as a highly controlled target thickness adjustment to establish a pristine, nanometer-thin silicon membrane while maintaining strict total thickness variation (TTV) control.

Once backside silicon polishing is complete, the wafer is handed off to downstream steps within the primary 40nm BSI CMOS Image Sensor process flow, including backside surface passivation, anti-reflective coating (ARC) deposition, trench isolation, and color filter array integration. Without precise thickness and surface execution at this junction, residual crystal damage or thickness non-uniformities directly degrade sensor electro-optical parameters, such as dark current and quantum efficiency.

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Upstream Input State

Before entering the backside silicon CMP module, the wafer stack undergoes several mechanical, thermal, and chemical operations that leave distinct structural and surface signatures:

• Wafer Bonding Strain and Bow: The device wafer is bonded face-to-face to a supporting carrier wafer. Differences in thermal expansion coefficients between multi-layer interconnect dielectrics, embedded metal lines, and silicon substrates generate internal stress, causing overall wafer warp and localized bowing.
• Subsurface Damage (SSD): Coarse mechanical grinding rapidly removes the bulk donor silicon. However, aggressive abrasive contact leaves micro-fractures, dislocation loops, and lattice disturbances extending several micrometers below the ground surface.
• Macro-Scale Total Thickness Variation (TTV): Coarse mechanical thinning exhibits high material removal rates but introduces spatial non-uniformities, frequently presenting a dome-shaped or edge-fast thickness distribution across the wafer diameter.
• Edge Topography: Following primary backside surface grinding, edge grinding operations round the wafer perimeter to mitigate chipping during subsequent handling, leaving a localized step-height boundary and stress concentration near the wafer edge.

The two-stage CMP process must systematically absorb these incoming structural non-uniformities, strip away the subsurface damage zone, and re-establish a flat plane parallel to the internal photodiode array.

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Physical and Chemical Mechanisms

Chemical mechanical planarization achieves wafer planarization through the synergistic combination of chemical surface modification and mechanical abrasion [P4]. The dual-stage CMP approach decouples high bulk material removal from atomic-scale surface polishing.

Incoming Ground Wafer (High Roughness & Subsurface Damage)
                         │
                         ▼
┌────────────────────────────────────────────────────────┐
│ Stage 1 (CMP1): Bulk Damage Stripping                  │
│ • High removal rate bulk polishing                     │
│ • Rapid removal of ground subsurface dislocations      │
│ • Multi-zone carrier pressure compensates macro-TTV    │
└────────────────────────────────────────────────────────┘
                         │
                         ▼
┌────────────────────────────────────────────────────────┐
│ Stage 2 (CMP2): Precision Target Thickness Adjust      │
│ • Alkaline colloidal silica slurry chemistry           │
│ • Surface hydration & passivation softens dynamic Si   │
│ • Microscale plastic removal prevents micro-fracturing │
│ • Sub-nanometer surface roughness (Ra) stabilization   │
└────────────────────────────────────────────────────────┘
                         │
                         ▼
┌────────────────────────────────────────────────────────┐
│ Real-Time Optical Metrology & Endpoint Control          │
│ • In-situ interferometric / spectral reflectivity      │
│ • Closed-loop thickness targeting to remaining Si      │
└────────────────────────────────────────────────────────┘
                         │
                         ▼
Backside Silicon Surface Ready for Passivation & Lithography

Primary Stage (CMP1): Bulk Silicon Removal and Damage Stripping

The first CMP stage targets a high material removal rate (MRR) to eliminate residual silicon above the photodiode region and clear deep subsurface damage:

• Bulk Removal Kinetics: Alkaline chemistries combined with sub-micron abrasives rapidly shear away the rough, mechanically disturbed silicon lattice.
• Profile Flattening: The polishing head utilizes multi-zone pneumatic back-pressure profiles. By applying higher local pressure to thicker concentric wafer zones, CMP1 flattens inherited dome or wedge profiles across the 300mm surface.

Secondary Stage (CMP2): Fine Polish and Target Thickness Adjustment

Once CMP1 brings the silicon membrane near its target window, the process shifts to the secondary CMP2 step for final thickness adjustment and surface smoothing:

• Chemical Hydration and Softening: In the secondary CMP2 precision polishing step, an alkaline colloidal silica slurry environment continuously hydrates and passivates the silicon surface, reducing its dynamic hardness so suspended nanoscale abrasives can gently shear away the softened material through microscale plastic removal without crystallographic fracturing.
• Defect-Free Polish: By avoiding direct mechanical fracturing, CMP2 removes residual micro-scratches and stabilizes surface roughness ($R_a$) to sub-nanometer levels, establishing an optically flat surface required for downstream anti-reflective coatings.

In-Situ Metrology and Endpoint Control

To achieve precise remaining silicon thickness (RST) across the wafer, in-situ optical monitoring is integrated into the polishing system:

• Interferometric Spectral Reflectance: Monochromatic or broadband light passes through a window in the polishing pad to illuminate the wafer backside. Light reflected from the top silicon surface interferes with light reflected from the buried silicon/dielectric interface.
• Phase Shift Model: The optical phase shift β depends on remaining silicon thickness $d$, refractive index $n$, and incident wavelength λ:

$$\beta = \frac{2\pi \cdot n \cdot d}{\lambda}$$

As the silicon thins, periodic interference fringes are generated and analyzed in real time to trigger polishing termination when the target membrane thickness is reached.

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Downstream Impact and Failure Propagation

Process variations during backside silicon CMP propagate directly into device performance and yield:

CMP Defect / Non-Uniformity	Direct Physical Consequence	Downstream Device Failure Mode
Remaining Silicon Thickness Non-Uniformity (High TTV / LTV)	Spatial variation in photon absorption path length across pixel array	Pixel-to-pixel quantum efficiency variations and color crosstalk
Residual Subsurface Damage (SSD)	High density of dislocation traps in active silicon volume	Elevated dark current, hot pixels, and dark random noise
High Surface Micro-Roughness	Light scattering at backside silicon interface	Decreased photon transmission and reduced peak sensitivity
Over-Polishing / Punch-Through	Structural erosion into underlying photodiode layers	Complete pixel deadness, electrical shorting, and catastrophic yield loss
Excessive Shear Stress	Mechanical strain propagated to bonding interface	Interfacial delamination or bond-pad micro-cracking

Optical Transmission and Quantum Efficiency

Silicon has a wavelength-dependent absorption depth. If remaining silicon thickness varies across the wafer, short-wavelength blue light may be absorbed before reaching the charge collection region in thicker areas, while long-wavelength red light passes completely through excessively thinned regions, causing spectral response non-uniformity.

Dark Current and White Pixels

Unremoved crystal dislocations act as mid-gap generation centers and metallic getter sites. Thermally generated carriers in damaged active silicon create high dark current and isolated "white pixel" defects under zero-illumination conditions.

Lithographic Focal Depth Limits

Subsequent lithography steps pattern backside deep trench isolation (BDTI), color filter grids, and microlenses. High local thickness variation distorts the local focal plane beyond scanner limits, leading to pattern bridging or linewidth variation.

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Walk the Real Step

In the operational BSI CIS manufacturing sequence, executing the CMP2 step requires precise coordination between head pressure zones, slurry chemistry, and optical metrology feedback.

To explore where this operation sits within the interactive manufacturing sequence, view the detailed step documentation:

• Open CIS Backside Si, CMP2 (target thickness adjust) in the interactive flow

During process execution, the bonded wafer is mounted face-down on a multi-zone carrier head against a polyurethane polishing pad. Colloidal silica slurry is delivered while active pressure zones compensate for residual radial thickness variations. As in-situ optical reflection metrology confirms that the target silicon thickness has been reached, polishing terminates, and the wafer transitions to post-CMP cleaning.

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Related Learning Paths

To examine how backside silicon polishing integrates with adjacent image sensor modules, explore these process flow articles:

• 40nm BSI CMOS Image Sensor process flow: A comprehensive overview of end-to-end sensor integration, from frontside pixel fabrication and hybrid bonding to backside finishing.
• 40nm BSI CMOS Image Sensor backside wafer thinning process flow: A detailed breakdown of the complete thinning module, including mechanical grinding, dual-stage CMP, wet etching, and surface passivation.

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Future Outlook

As BSI pixel pitches scale below one micrometer, backside thickness control faces narrower process windows. Key technical developments focus on:

• Integrated CMP and Plasma Compensatory Etching: Pairing CMP thickness mapping with localized downstream plasma etching to compensate for residual spatial non-uniformities across 300mm wafers.
• Broadband Multi-Layer Spectral Profiling: Upgrading single-wavelength interferometers to broadband spectral algorithms capable of resolving complex dielectric stack reflections beneath thin silicon membranes.
• Selective Chemical Polish Buffers: Developing chemistries that exhibit reduced removal rates on heavily doped epitaxial silicon stop layers to improve final remaining silicon thickness uniformity.