Function in the Complete Flow
In a 40nm backside illumination (BSI) CMOS image sensor (CIS), shallow trench isolation (STI) chemical mechanical planarization (CMP) acts as the critical bridge between primary trench isolation formation and active device patterning , . The process receives a wafer surface characterized by deep topographies: etched silicon substrate trenches filled with overburden silicon dioxide deposited over a protective silicon nitride stop layer and underlying pad oxide , . The core objective of 40nm BSI CMOS image sensor STI CMP is to systematically remove the excess blanket dielectric overburden across the entire wafer surface, achieving both global and local planarization while stopping precisely on the thin hardmask layer , .
Once planarization is completed, the process hands off a smooth, highly flat surface flush with the hardmask to downstream modules . This handoff is vital for subsequent pad nitride stripping, well ion implantations, and gate stack lithography , . In a BSI architecture, where light enters through the thinned substrate reverse side while read-out electronics reside on the front side, maintaining perfect surface planarity and zero structural damage on the front side is paramount . The pixel array demands extreme cross-wafer removal uniformity and minimal defectivity to eliminate localized dark current generation centers . Concurrently, the peripheral logic circuit region requires robust isolation boundaries to suppress cross-talk, withstand high switching frequencies, and support high-density transistor integration . Consequently, pixel isolation CMP integration serves as the gatekeeper for both optical baseline performance and peripheral logic functionality , .
For a detailed structural overview of the entire front-end fabrication chain, refer to the 40nm BSI CMOS Image Sensor process flow .
Guided route
STI CMP
This article maps to Chapter 1 (Isolation) of the 40nm BSI structural spine — 6 stops through the complete flow, each with rationale and 2.5D cross-section evolution.
- 1IsolationThis article
- 2Photosensitive junction
- 3Bonding
- 4Thinning
- 5Color selection
- 6Light focusing
Upstream Input State
Prior to shallow trench isolation planarization in CIS, the wafer undergoes a sequence of front-end substrate patterning and deposition operations , . First, a thin pad oxide layer is thermally grown on the silicon substrate to alleviate interfacial stress, followed by the chemical vapor deposition (CVD) of a silicon nitride stopping layer , . Photoresist mask patterning and plasma reactive ion etching then carve shallow trenches into the silicon substrate , . To prevent sharp geometric corners that generate intense localized electric fields, thermal liner oxidation and corner rounding treatments are performed on the etched trench sidewalls and rims .
Following liner formation, high-density plasma CVD or sub-atmospheric CVD fills the trenches with silicon dioxide . Because dielectric deposition is inherently non-selective, a substantial oxide overburden accumulates across both the narrow isolation trenches and the active silicon regions . This creates a severe step-height topography that mirrors the underlying pattern layout , .
Upstream Topography Prior to STI CMP:
Overburden Oxide Fill (Topography Step-Height)
+-------------------------------------------------+
| +---+ Field Oxide Overburden +---+ |
+--+ | +--------------------------+ | +----+
| Nitride Stop | | Nitride Stop|
+--------------+ +-------------+
| Pad Oxide | Shallow Trench | Pad Oxide |
+--------------+ (Substrate Si) +-------------+
| Silicon Substrate |
+---------------------------------------------------+
The incoming state presents a pronounced contrast in pattern density between different functional domains on the chip (Engineering Practice):
- Pixel Array Domain: Highly repetitive, uniform arrays of small active photodiode nodes separated by narrow isolation trenches .
- Periphery Domain: Highly irregular pattern densities comprising broad active regions for digital logic, analog signal processing, and wide isolation fields , .
This substantial height variation and spatial non-uniformity in pattern density generate localized pressure gradients during CMP polish, making incoming planarity control a primary determinant of polishing behavior , .
Physical and Chemical Mechanisms
The fundamental operation of STI CMP relies on synergistic chemical reaction kinetics and mechanical abrasion, frequently described as a chemical softening followed by mechanical removal process . Material removal rate (MRR) is governed at the micro-scale by the Prestonian interaction between polish pad properties, slurry abrasive dynamics, applied down-force, and relative sliding velocity .
Chemical-Mechanical Synergistic Removal Mechanism:
Polishing Down-Force & Sliding Motion (Pad & Slurry Abrasives)
│
▼
┌──────────────────────────────────────────────┐
│ Chemical Surface Softening / Hydroxylation │ <-- Slurry Chemistry / CeO2 Reaction
└──────────────────────┬───────────────────────┘
│
▼
┌──────────────────────────────────────────────┐
│ Shear-Based Mechanical Abrasion │ <-- Abrasive Contact Shear Stress
└──────────────────────┬───────────────────────┘
│
▼
┌──────────────────────────────────────────────┐
│ Passivated Silicon Nitride Stop Layer │ <-- Selective Surfactant Adsorption
└──────────────────────────────────────────────┘
In 40nm shallow trench isolation CMP, high-selectivity slurries utilizing ceria ($CeO_2$) particles are predominantly employed . Ceria abrasives exhibit chemical reactivity toward silicon dioxide due to surface oxygen vacancies and variable cerium oxidation states . Ce-O-Si chemical bonds form transiently at the liquid-solid interface, significantly lowering the activation energy required to break the silicate network . Mechanical shear forces exerted by the moving polishing pad then dislodge the chemically softened oxide surface layer .
To achieve high oxide-to-nitride removal selectivity, chemical additives such as non-ionic polymers or anionic surfactants are formulated into the slurry , . The fundamental formula governing polishing selectivity is expressed as:
$$\text{Selectivity} = \frac{\text{MRR}{\text{oxide}}}{\text{MRR}{\text{nitride}}}$$
Under specific slurry pH conditions, electrostatic charge differences develop between the oxide and nitride surfaces . Silicon nitride surfaces adsorb surfactant molecules preferentially, forming a protective, self-assembled boundary lubrication film . This passivating layer shields the underlying silicon nitride hardmask from physical contact with abrasive particles, dampening mechanical wear . Conversely, the silicon dioxide film remains uninhibited, allowing rapid oxide clearing until the polish pad clears the overburden and contacts the protected nitride surface , .
However, local pattern density variations severely disturb uniform planarization mechanics , . In wide oxide field regions within the peripheral logic, high local pressure causes the flexible polishing pad to flex downward, removing oxide below the surrounding active surface plane—a defect known as dishing , . In dense active areas, the high concentration of small nitride features bears excessive localized down-force, leading to unwanted polish-through and erosion of the nitride hardmask edges , . Balancing dishing against erosion requires precise tuning of slurry rheology, pad hardness, and carrier multi-zone pressure distribution .
For a deep dive into the integration sequence surrounding these physical steps, see the 40nm BSI CMOS Image Sensor shallow trench isolation process flow .
Downstream Impact and Failure Propagation
Inadequate process margin during planarization triggers critical failure modes that propagate directly into both pixel and peripheral performance , .
Failure Propagation Pathways in 40nm BSI CIS:
STI CMP Over-Polish / Nitride Erosion
│
├──────────────────────────────────────────────┐
▼ ▼
Trench Edge Recess & Active Corner Exposure Asymmetric Oxide Dishing
│ │
▼ ▼
Corner Field Concentration / Subthreshold Hump Photolithography Depth-of-Focus Error
│ │
▼ ▼
Dark Current Leakage & White Pixel Defects Gate Length Defocus & Timing Jitter
1 [P4]. Pixel Array Reliability and Optical Dark Performance
In a CMOS image sensor, the pixel photodiode must maintain an extraordinarily low noise floor . If the STI CMP step causes excessive erosion of the nitride hardmask or creates severe oxide recess along the trench edges, the upper corners of the active silicon substrate become exposed , . Subsequent wet etching steps to strip the pad nitride further exacerbate this recess, forming sharp silicon corners . During operational bias, the electric field concentrates intensely at these sharp trench corners , . This corner field enhancement lowers the threshold voltage locally, inducing parasitic subthreshold conduction paths (often observed as a double-hump in transfer characteristics) . Furthermore, structural damage and dangling bonds at the exposed corner interface act as thermal generation centers, injecting unwanted carriers into the pinned photodiode . This directly manifests as elevated dark current, hot pixels, and fixed pattern noise across the image sensor array .
2. Micro-Scratches and White Pixel Defects
Mechanical force transferred by agglomerated ceria particles can induce sub-surface micro-scratches within the trench oxide or adjacent active silicon . In BSI sensors, deep micro-scratches or embedded slurry contaminants act as severe recombination-generation traps (Engineering Practice). During long integration times, these localized defect sites continuously generate electron-hole pairs, producing bright, fully saturated individual pixels known as white pixels that destroy image fidelity .
3. Periphery Transistor Performance and Photolithography Margins
In the peripheral logic circuits, severe dishing in wide dielectric isolation areas leads to localized step-height variations , . When the wafer proceeds to gate pattern lithography, these topography variations exceed the narrow depth-of-focus window inherent to short-wavelength photolithography tools (Engineering Practice). As a result, gate photoresist lines over dished regions suffer from critical dimension variation, necking, or bridging, causing timing jitter, threshold shifts, or complete logic failure , . Furthermore, if CMP fails to clear oxide overburden completely from dense active regions, residual oxide blocks subsequent wet stripping of the silicon nitride stop layer, causing active area patterning defects and complete transistor failure .
Walk the Real Step
During full manufacturing, operators and process integration engineers monitor the planarization module via real-time process control parameters . The process sequence is anchored by precise endpoint detection systems that track motor current load changes or optical reflectivity shifts as the polishing interface transitions from overburden oxide to the hardmask surface , .
To examine the exact execution parameters, equipment operational sequences, and recipes within the complete flow, Open STI Step 42 in the interactive flow (Engineering Practice).
Within Step 42, chemical slurry delivery, multi-zone head pressure adjustments, and post-CMP megasonic cleaning are combined to ensure zero slurry residue and zero micro-scratch formation across both the pixel matrix and peripheral device regions .
Related Learning Paths
To further expand your understanding of advanced image sensor integration and front-end isolation modules, explore these connected engineering guides:
- 40nm BSI CMOS Image Sensor Process Flow: Integration Principles, Device Physics, and Module Dependencies — Comprehensive overview of the complete BSI sensor manufacturing module sequence from substrate preparation to back-end metallization .
- 40nm BSI CMOS Image Sensor Shallow Trench Isolation Process Flow: Integration Logic, Mechanisms, and Engineering Tradeoffs — Detailed breakdown of trench etching, liner oxidation, oxide gap fill, and post-isolation thermal treatments .
Future Outlook
As BSI CMOS image sensors scale beyond the 40nm node into sub-micron pixel pitches, conventional planar shallow trench isolation reaches severe physical limits . Extreme scaling reduces photodiode volume, decreasing full-well capacity and sensitivity . To preserve pixel area while ensuring complete electrical and optical cross-talk suppression, modern CIS architectures are transitioning toward deep trench isolation (DTI) and back-side deep trench isolation (BDTI) modules .
These advanced isolation schemes mandate multi-step CMP operations where high aspect-ratio silicon trenches filled with poly-silicon, metal oxides, or composite dielectrics must be planarized without inducing stress-induced silicon dislocation defects , . Emerging CMP developments center on fixed-abrasive pads, ultra-low down-force polishing heads, and molecularly engineered chemical additives that provide near-infinite polish selectivity, ensuring defect-free planar interfaces for next-generation image sensors , .