Selective Si and SiGe Epitaxy Integration at 14nm: Principles, Strain Kinetics, and Integration Logic

Function in the Complete Flow

In modern 14nm FinFET logic fabrication, raised source/drain epitaxy plays a foundational role by simultaneously managing parasitic series resistance, channel stress engineering, and sacrificial contact material. Single-crystal silicon fins in 14nm architectures possess an extremely narrow cross-sectional geometry, rendering direct contact formation on raw fins susceptible to severe parasitic access resistance and catastrophic silicon channel consumption during downstream silicidation.

Extrinsic source and drain series resistances cannot be modulated by gate bias and induce parasitic voltage drops that degrade overall transistor transconductance and drive current. To overcome these device constraints, raised source and drain epitaxy is executed after S/D recess etching, refilling the recessed fin cavities with heavily doped single-crystal semiconductor material.

For p-channel transistors (pMOS), the module incorporates a high-germanium-content, boron-doped silicon-germanium (SiGe) material stack to serve as an embedded channel stressor. Because the natural lattice constant of bulk SiGe exceeds that of underlying silicon, the embedded S/D epitaxy exerts a uniaxially compressive strain along the fin channel length. Compressive strain in the channel modifies the valence-band structure by reducing hole effective mass, thereby enhancing carrier mobility and increasing drive current without aggressive threshold-voltage scaling. For n-channel transistors (nMOS), silicon or carbon-doped silicon in situ doped with phosphorus is selectively grown to minimize contact resistance while maintaining shallow junction profiles.

In an advanced CMOS process flow, the CMOS epi module is inserted after extension/halo formation, before the deposition of the interlayer dielectric (ILD0) and replacement metal gate (RMG) module [P1]. Positioned strategically within the broader 14nm FinFET process flow, this step receives recessed fin cavities bounded by gate sidewall dielectric spacers and delivers precisely faceted, heavily doped single-crystal contact regions to downstream silicidation and contact metallization modules. Its placement prior to the third spacer deposition module is critical because the epitaxial source/drain geometry and stressor profile must be fully finalized before forming additional sidewall spacers that isolate the source/drain regions and define downstream contact alignment.

Upstream Input State

Prior to entering the epitaxy chamber, the wafer undergoes anisotropic dry etching to create recessed source/drain cavities within the active silicon fin arrays. The physical state inherited by the epitaxy tool exhibits a multi-material surface topology consisting of exposed single-crystal silicon fin faces ({100}, {110}, and {113} crystallographic planes), amorphous silicon nitride gate sidewall spacers, and oxide shallow trench isolation (STI) regions.

The atomic cleanliness and structural integrity of the exposed single-crystal silicon surfaces are paramount for defect-free crystalline seeding. Upstream dry-etching operations inevitably leave behind native oxide layers, surface lattice damage, artificial oxide skins, and halide etching residues along the recessed fin sidewalls and cavity floors. If unaddressed, surface oxygen atoms disrupt incoming adatom lattice alignment, resulting in epitaxial dislocation networks, polycrystalline growth, or total amorphous nucleation failure.

To prepare the surface, a dedicated chemical etch step for the removal of artificial oxide skins is performed prior to entering the epitaxial growth system. Once inside the epitaxy chamber, an in situ low-temperature thermal desorption prebake in a reducing hydrogen atmosphere precedes semiconductor gas injection to remove any remaining oxide skin traces. However, the thermal budget during prebaking must be strictly bounded to prevent physical structural distortion or reflow of the delicate silicon fins.

Physical and Chemical Mechanisms

Selective deposition means that the silicon deposits on exposed regions of silicon, but not on other films, such as silicon dioxide or silicon nitride [T1]. Operating under reduced-pressure chemical vapor deposition (RPCVD) kinetics, selective epitaxy relies on maintaining a rigorous thermodynamic and kinetic balance between chemical deposition on single-crystal silicon surfaces and chemical etching on adjacent dielectric surfaces.

During SiGe epi growth, gaseous precursors such as dichlorosilane or silane for silicon, germane for germanium, and diborane for p-type dopants are injected into the reactor alongside hydrochloric acid (HCl) as a selectivity-enabling etchant. Precursor adatoms adsorb onto exposed single-crystal silicon fin surfaces and migrate across the atomic surface to occupy low-energy lattice sites, continuing the underlying crystal lattice template.

Conversely, on amorphous dielectric surfaces such as silicon nitride spacers or STI oxides, adatom adsorption energy is significantly lower, causing species to nucleate as isolated, weakly bound amorphous clusters. Hydrochloric acid selectively attacks these unstable dielectric surface clusters at a kinetic etching rate far exceeding the epitaxial deposition rate on single-crystal silicon. As a result, nucleation on dielectrics is suppressed while continuous epitaxial growth proceeds on the fin surfaces.

From a solid-state physics standpoint, embedded SiGe introduces uniaxial compressive strain into the channel due to lattice constant mismatch. This mechanical stress breaks the valence band degeneracy at the Brillouin zone center, splitting the heavy-hole and light-hole energy bands while reducing interband hole scattering. Concurrently, anisotropic growth kinetics across crystal orientations lead to dominant facet formation along low-growth-rate planes such as {111} and {113}, producing signature diamond-shaped (sigma-shape) epitaxial profiles that optimize stress proximity to the channel while controlling lateral spacer encroachment.

Downstream Impact and Failure Propagation

The geometric, structural, and compositional characteristics established during S/D epitaxy directly dictate downstream module process windows and final transistor electrical behavior in the 14nm FinFET process flow.

Directional trade-offs during epitaxial growth introduce complex architectural balances:

• Epitaxial Merging vs. Parasitic Capacitance: Extending lateral epitaxial growth allows adjacent fin structures to merge into a unified contact pad, expanding total contact surface area and significantly reducing source/drain series resistance. However, excessive lateral expansion increases parasitic gate-to-source/drain overlap capacitance and elevates the risk of shorting to adjacent gate structures.
• Prebake Thermal Budget Limits: Excessively high thermal prebake temperatures or prolonged thermal exposure cause silicon fin reflow, corner rounding, and undesired dopant redistribution from prior implantation modules.
• Selectivity Etchant Balance: Insufficient hydrochloric acid partial pressure results in non-selective parasitic nucleation on gate sidewall spacers, establishing direct electrical bridge shorts between gate and source/drain terminals. Conversely, excessive hydrochloric acid flow induces undesired chemical etching of the underlying silicon fin cavity, distorting the recessed template.

Failure modes propagate directly into device electrical degradation:

• Strain Relaxation via Dislocation Formation: If the germanium fraction in SiGe selective epi exceeds the critical layer thickness for elastic strain accommodation, misfit dislocations generate at the heterojunction interface. These dislocations act as carrier generation-recombination centers, increasing junction leakage current while degrading strain-induced mobility gains.
• Pattern Dependency and Micro-Loading: Variations in exposed silicon pattern density across dense and isolated circuit layouts alter local precursor consumption rates. This micro-loading effect causes spatial non-uniformity in epitaxy height, germanium content, and dopant incorporation, manifesting as threshold voltage variations across the die.

Walk the Real Step

To examine how this epitaxy step operates inside a high-volume manufacturing flow, view the step details directly: Open the interactive flow step details.

Within this process module, selective Si and SiGe source/drain epitaxy is performed inside an automated RPCVD single-wafer multi-chamber cluster system. The operational sequence begins with an in situ thermal desorption bake under hydrogen flow to desorb thin native oxides without altering the narrow silicon fin geometry. Once surface clean verification is complete, process gas flows—including silicon precursors, germanium precursors, in situ dopants, and hydrochloric acid—are stabilized under low pressure and controlled thermal conditions. Deposition and etching kinetics occur simultaneously, building faceted, highly doped single-crystal semiconductor regions confined by sidewall spacers. Real-time control of partial pressure ratios and spatial thermal distribution ensures uniform epitaxy height and strain performance across diverse pattern density regions on the wafer.

Related Learning Paths

The selective epitaxy module operates in close coordination with adjacent front-end and middle-of-line integration steps:

• Recess Etching Module: Upstream dry-etching defines cavity depth, sidewall orientation, and surface clean requirements inherited by the epitaxy chamber.
• Replacement Metal Gate (RMG) Module: Thermal budget constraints during epitaxy protect dummy gate and sidewall spacer integrity, ensuring subsequent high-k metal gate stack deposition remains uncompromised as detailed in the 14nm FinFET Replacement Metal Gate Integration Process Flow.
• Contact Silicidation Module: Raised source/drain epitaxy provides sacrificial single-crystal material consumed during silicide formation, preventing metal encroachment into the active channel region.
• Chemical Mechanical Planarization (CMP) Modules: Downstream inter-layer dielectric planarization covered in the 14nm FinFET Contact Etch-Stop and Pre-Metal Dielectric Integration Process Flow relies on consistent epitaxy height profiles to avoid over-polishing or contact under-etching.

Future Outlook

As device architectures scale past the 14nm FinFET node into gate-all-around (GAA) nanosheets and complementary field-effect transistors (CFETs), selective epitaxy mechanisms face increasingly complex physical requirements. In nanosheet architectures, selective epitaxy is leveraged not only for raised source/drain strain engineering but also for alternating sacrificial layer growth and inner spacer formation within highly confined horizontal channels. Mastering atomic-scale kinetic selectivity, micro-loading suppression, and abrupt dopant profiling across three-dimensional geometries represents the cornerstone of continued logic scaling.