Selective Si and SiGe Epitaxy Integration at 14nm: Principles, Strain Kinetics, and Integration Logic

Function in the Complete Flow

14nm epitaxial silicon source-drain integration plays a foundational role in modern field-effect transistor (FinFET) logic fabrication by simultaneously managing series resistance, channel stress engineering, and sacrificial silicide contact material [T2], [T3]. In a 14nm FinFET architecture, single-crystal silicon fins possess an extremely narrow cross-sectional geometry, rendering direct contact formation on raw fins susceptible to severe parasitic access resistance and silicon channel consumption [T3], [A1]. To resolve these fundamental device constraints, raised source drain epitaxy 14nm is executed following source/drain (S/D) recess etching, growing heavily doped elevated crystal structures directly upon exposed fin cavity surfaces [P1], [A1].

For p-channel metal-oxide-semiconductor (pMOS) devices, the module incorporates a high-germanium-content, boron-doped silicon-germanium (SiGe) material stack via SiGe selective epi to serve as an embedded channel stressor [P1], [P2]. Because the natural lattice constant of bulk SiGe exceeds that of underlying silicon, the grown S/D epitaxy exerts a uniaxially compressive strain along the fin channel length, altering the electronic band structure to lower hole effective mass and boost drive current [P1], [P3]. For n-channel metal-oxide-semiconductor (nMOS) devices, silicon or carbon-doped silicon in situ doped with phosphorus is selectively grown to minimize contact resistance while maintaining shallow junction profiles [T3], [A1]. Placed strategically within the broader 14nm FinFET process flow, this step receives recessed fin cavities bounded by gate sidewall dielectric spacers and delivers precisely faceted, heavily doped single-crystal contact regions to downstream silicidation and contact metallization modules [P1], [A1].

Upstream Input State

Prior to entering the epitaxy module, the wafer undergoes anisotropic dry etching to create recessed source/drain cavities within the active silicon fin arrays [A1], [A2]. The physical state inherited by the epitaxy tool exhibits a complex, multi-material surface topology consisting of exposed single-crystal silicon fin faces ({100}, {110}, and {113} crystallographic planes), amorphous silicon nitride gate sidewall spacers, and oxide shallow trench isolation (STI) regions [P2], [P3].

The atomic cleanliness and structural integrity of the exposed single-crystal silicon surfaces are paramount for crystalline seeding [P1], [T2]. Upstream dry-etching operations inevitably leave behind native oxide layers, surface lattice damage, and halide etching residues along the recessed fin sidewalls and cavity floors [P1], [P2]. If unaddressed, surface oxygen atoms disrupt incoming adatom lattice alignment, resulting in epitaxial dislocation networks, polycrystalline growth, or total amorphous nucleation failure [P2], [T2]. Consequently, an in situ surface preparation combining chemical oxide desorption and a low-temperature thermal prebake in a reducing hydrogen environment must precede semiconductor gas injection [P1], [T2]. However, the thermal budget during prebaking must be strictly bounded to prevent physical structural distortion or reflow of the delicate 14nm silicon fins [P1], [P2].

Physical and Chemical Mechanisms

The fundamental principle governing this module is the selective epitaxy mechanism FinFET operating under reduced pressure chemical vapor deposition (RPCVD) kinetics [P1], [P2]. Selective epitaxy relies on maintaining a rigorous thermodynamic and kinetic balance between chemical deposition on single-crystal silicon surfaces and chemical etching on adjacent dielectric surfaces [P1], [P2], [T1].

During SiGe epi growth integration, gaseous precursors such as dichlorosilane or silane for silicon, germane for germanium, and diborane for p-type dopants are injected into the reactor alongside hydrochloric acid as a selectivity-enabling etchant [P1], [P2], [T2]. Precursor adatoms absorb onto exposed single-crystal silicon fin surfaces and migrate across the atomic surface to occupy low-energy lattice sites, continuing the underlying crystal lattice template [P2], [T1].

Conversely, on amorphous dielectric surfaces such as silicon nitride spacers or STI oxides, adatom adsorption energy is significantly lower, causing species to nucleate as isolated, weakly bound amorphous clusters [P2], [T1]. Hydrochloric acid selectively attacks these unstable dielectric surface clusters at a kinetic etching rate far exceeding the epitaxial deposition rate on single-crystal silicon [P1], [P2], [T1]. As a result, nucleation on dielectrics is entirely suppressed while continuous epitaxial growth proceeds on the fin surfaces [P1], [P2].

From a solid-state physics standpoint, embedded SiGe introduces uniaxial compressive strain into the channel due to lattice constant mismatch [P1], [P3]. This mechanical stress breaks the valence band degeneracy at the Brillouin zone center, splitting the heavy-hole and light-hole energy bands while reducing interband hole scattering [P3], [T3]. Concurrently, anisotropic growth kinetics across crystal orientations lead to dominant facet formation along low-growth-rate planes such as {111} and {113}, producing signature diamond-shaped (sigma-shape) epitaxial profiles that optimize stress proximity to the channel while controlling lateral spacer encroachment [P2], [P3].

Downstream Impact and Failure Propagation

The geometric, structural, and compositional characteristics established during S/D epitaxy directly dictate downstream module process windows and final transistor electrical behavior in the 14nm FinFET process flow integration [P1], [A1].

Directional trade-offs during epitaxial growth introduce complex architectural balances:

• Epitaxial Merging vs [P2]. Parasitic Capacitance: Extending lateral epitaxial growth allows adjacent fin structures to merge into a unified contact pad, expanding total contact surface area and significantly reducing source/drain series resistance [A1], [A2]. However, excessive lateral expansion increases parasitic gate-to-source/drain overlap capacitance and elevates the risk of shorting to adjacent gate structures [P2], [A1].
• Prebake Thermal Budget Limits: Excessively high thermal prebake temperatures or prolonged thermal exposure cause silicon fin reflow, corner rounding, and undesired dopant redistribution from prior implantation modules [P1], [P2].
• Selectivity Etchant Balance: Insufficient hydrochloric acid partial pressure results in non-selective parasitic nucleation on gate sidewall spacers, establishing direct electrical bridge shorts between gate and source/drain terminals [P1], [P2]. Conversely, excessive hydrochloric acid flow induces undesired chemical etching of the underlying silicon fin cavity, distorting the recessed template [P2].

Failure modes propagate directly into device electrical degradation:

• Strain Relaxation via Dislocation Formation: If the germanium fraction in SiGe selective epi exceeds the critical layer thickness for elastic strain accommodation, misfit dislocations generate at the heterojunction interface [P3]. These dislocations act as carrier generation-recombination centers, increasing junction leakage current while degrading strain-induced mobility gains [P3].
• Pattern Dependency and Micro-Loading: Variations in exposed silicon pattern density across dense and isolated circuit layouts alter local precursor consumption rates [P2], [P3]. This micro-loading effect causes spatial non-uniformity in epitaxy height, germanium content, and dopant incorporation, manifesting as threshold voltage variations across the die [P2], [P3].

Walk the Real Step

To examine how this epitaxy step operates inside a high-volume manufacturing flow, view the step details directly: Open SD_ESI Step 124 in the interactive flow [P2].

Within Step 124, selective Si and SiGe source/drain epitaxy is performed inside an automated RPCVD single-wafer multi-chamber cluster system [P2]. The operational sequence begins with an in situ thermal desorption bake under hydrogen flow to desorb thin native oxides without altering the narrow silicon fin geometry [P1], [P2]. Once surface clean verification is complete, process gas flows—including silicon precursors, germanium precursors, in situ dopants, and hydrochloric acid—are stabilized under low pressure and controlled thermal conditions [P1], [T2]. Deposition and etching kinetics occur simultaneously, building faceted, highly doped single-crystal semiconductor regions confined by sidewall spacers [P1], [P2], [A1]. Real-time control of partial pressure ratios and spatial thermal distribution ensures uniform epitaxy height and strain performance across diverse pattern density regions on the wafer [P1], [P2].

Related Learning Paths

The selective epitaxy module operates in close coordination with adjacent front-end and middle-of-line integration steps:

• Recess Etching Module: Upstream dry-etching defines cavity depth, sidewall orientation, and surface clean requirements inherited by the epitaxy chamber [A1], [A2].
• Replacement Metal Gate (RMG) Module: Thermal budget constraints during epitaxy protect dummy gate and sidewall spacer integrity, ensuring subsequent high-k metal gate (HKMG) stack deposition remains uncompromised [P1], [A1].
• Contact Silicidation Module: Raised source/drain epitaxy provides sacrificial single-crystal material consumed during silicide formation, preventing metal encroachment into the active channel region [T2], [T3].
• Chemical Mechanical Planarization (CMP) Modules: Downstream inter-layer dielectric planarization relies on consistent epitaxy height profiles to avoid over-polishing or contact under-etching [A1], [A2].

Future Outlook

As device architectures scale past the 14nm FinFET node into gate-all-around (GAA) nanosheets and complementary field-effect transistors (CFETs), selective epitaxy mechanisms face increasingly complex physical requirements [P3]. In nanosheet architectures, selective epitaxy is leveraged not only for raised source/drain strain engineering but also for alternating sacrificial layer growth and inner spacer formation within highly confined horizontal channels [P3]. Mastering atomic-scale kinetic selectivity, micro-loading suppression, and abrupt dopant profiling across three-dimensional geometries represents the cornerstone of continued logic scaling [P2], [P3].